Reconfigurable delta sigma analog-to-digital converter and customized digital filters with embedded flash FPGA and flash memory

1. An integrated circuit comprising:

at least one analog input;

a sample/hold circuit coupled to the at least one analog input;

a reconfigurable delta-sigma ADC coupled to the sample/hold circuit;

a field programmable gate array coupled to the reconfigurable delta-sigma ADC; and

a configurable on-chip clock source coupled to the reconfigurable delta-sigma ADC.

2. The integrated circuit of claim 1 wherein the at least one analog input comprises a plurality of analog inputs coupled to an analog multiplexer, an output of the analog multiplexer coupled to the sample/hold circuit.

3. The integrated circuit of claim 2 wherein the output of the analog multiplexer is coupleable to the sample/hold circuit through an analog buffer.

4. The integrated circuit of claim 3 wherein the analog buffer has single-ended outputs and differential outputs.

5. The integrated circuit of claim 4 wherein the single-ended outputs and differential outputs of the analog buffer are selectively coupleable to the sample/hold circuit.

6. The integrated circuit of claim 1 wherein the configurable on-chip clock source comprises:

a clock-source multiplexer having an output;

a crystal oscillator coupled to a first input of the clock-source multiplexer;

a RC oscillator coupled to a second input of the clock-source multiplexer;

wherein an output of the clock-source multiplexer is coupled to the field programmable gate array, the sample/hold circuit, and the reconfigurable delta-sigma ADC.

7. The integrated circuit of claim 1 further comprising:

a real-time clock coupled to a crystal oscillator;

a JTAG control line coupled to the real-time clock;

at least one external-device control line coupled to the real-time clock; and

at least one configuration and control line coupled between the real-time clock and the field programmable gate array.

8. The integrated circuit of claim 1 further comprising a phase locked loop selectively coupled to the on-chip clock source.

9. The integrated circuit of claim 1 wherein:

the on-chip clock source comprises:

a clock-source multiplexer having an output;

a crystal oscillator coupled to a first input of the clock-source multiplexer;

a RC oscillator coupled to a second input of the clock-source multiplexer;

wherein an output of the clock-source multiplexer is coupled to the field programmable gate array, the sample/hold circuit, and the reconfigurable delta-sigma ADC;

the integrated circuit further comprising a phase-locked loop selectively coupled to the output of the on-chip clock source.

10. The integrated circuit of claim 9 wherein:

the integrated circuit further includes a phase-locked loop multiplexer having a first input coupled to the output of the clock-source multiplexer; and

the phase locked loop is coupled to the output of the clock-source multiplexer and to a second input of the phase-locked loop multiplexer.

11. The integrated circuit of claim 1 wherein the configurable on-chip clock source is coupled to an analog clock source that drives the sample/hold circuit and the reconfigurable delta-sigma ADC.

12. The integrated circuit of claim 11 wherein the analog clock source is selectively enabled by a signal from the field-programmable gate array.

13. The integrated circuit of claim 1 further including a digital-to-analog converter coupled to the field-programmable gate array.

14. The integrated circuit of claim 1 , wherein:

the reconfigurable delta-sigma ADC further comprises:

a hardwired digital filter; and

digital filter bypass circuitry to bypass the hardwired digital filter.

15. The integrated circuit of claim 14 , wherein:

the digital filter bypass circuitry is coupled to the field programmable gate array.

16. The integrated circuit of claim 15 , wherein:

the field programmable gate array is programmed to implement a digital filter.