Programmable delay line compensated for process, voltage, and temperature

1. A programmable delay line compensated for process, voltage, and temperature variations in an integrated circuit, comprising:

a source of programming data;

a delay locked loop (DLL) configured to delay a digital signal by the clock period of the clock signal, the DLL including a DLL delay line arranged as a plurality of cascaded sub-delay lines each sub-delay line providing one of a plurality of delays in response to a digital control signal wherein the number of active sub-delay lines is determined in response to the source of programming data;

a fractionating circuit configured to generate a digital signal delay line control signal that is a fraction of the digital control signal in response to the source of programming data; and

a digital signal delay line arranged as a plurality of cascaded sub-delay lines each sub-delay line providing one of a plurality of delays in response to the digital signal delay line control signal.

2. The delay line of claim 1 wherein:

the digital control signal is generated by a plurality of multi-bit counters controlled by a count sequence controller and having an output coupled to a corresponding one of the sub-delay elements; and

the fractionating circuit comprises a masking circuit that selectively masks the outputs of selected ones of the counters to generate the digital signal delay line control signal.

3. The delay line of claim 2 wherein each sub-delay line comprises a plurality of delay quanta connected between a minimum delay node and a maximum delay node, wherein the input node and the output of each delay quanta is coupled to data inputs of a delay multiplexer.

4. The delay line of claim 2 wherein the count sequence controller enables counters in order from the counter controlling the first one of the cascaded sub-delay lines.

5. The delay line of claim 1 wherein the DLL delay line is longer than the digital signal delay line.

6. The delay line of claim 1 wherein:

the digital control signal is generated by a master multi-bit up/down counter having an output driving a binary to multi-line decoder; and

the fractionating circuit comprises a binary to multi-line decoder driven by the output of the master multi-bit up/down counter and driving a masking circuit that selectively masks the outputs of selected ones of the counters to generate the digital signal delay line control signal.

7. The delay line of claim 1 wherein:

the digital control signal is generated by a master multi-bit up/down counter having an output driving a binary to multi-line decoder; and

the fractionating circuit comprises a multiplier generating a product of the output of the master multi-bit up/down counter and a multi-bit digital number.

8. The delay line of claim 7 wherein the product of the output of the master multi-bit up/down counter and the multi-bit digital number is truncated to a selected number of most significant bits.

9. The delay line of claim 2 , further including a set of latches coupled between the masking circuit and the digital signal delay line.

10. The delay line of claim 1 wherein the fraction of the digital control signal has a denominator equal to the number of sub-delay elements used in the DLL delay line and a numerator equal to the number of sub-delay elements used in the digital signal delay line.

11. The delay line of claim 1 wherein the digital signal delay line is a clock signal delay line.