Programming method for non-volatile memory and non-volatile memory-based programmable logic device

1. An integrated circuit comprising:

an array of flash memory cells organized into rows and columns, each cell in each row coupled to a row line and a column line;

a programming circuitry for programming the array of flash memory cells, said programming circuitry implementing a method for programming the array of flash memory cells, comprising:

performing a gate disturb on the flash memory cells;

if cells fail to meet a predetermined threshold following the gate disturb, recording data for the cells;

performing a column disturb on the flash memory cells;

if cells fail to meet a predetermined threshold following the column disturb, recording data for the cells; and

determining at least one programming parameter based on the recorded data.

2. The integrated circuit of claim 1 , wherein the method further comprises:

programming selected ones of the flash memory cells using the programming parameter.

3. The integrated circuit of claim 2 , wherein:

programming selected ones of the flash memory cells using the programming parameter includes programming the selected ones of the flash memory cells to control the configuration of a programmable logic device.

4. The integrated circuit of claim 3 , wherein:

the programmable logic device is a field programmable gate array.

5. The integrated circuit of claim 1 , wherein the method further comprises:

erasing the flash memory cells before performing the gate disturb; and

erasing the flash memory cells before performing the column disturb.

6. The integrated circuit of claim 5 , wherein the method further comprises:

verifying the erasing of the flash memory cells before performing the gate disturb; and

verifying the erasing of the flash memory cells before performing the column disturb.

7. The integrated circuit of claim 1 , wherein:

the flash memory cells are disposed on a semiconductor die, and

the method further comprising:

storing at least one programming parameter in a memory disposed on the semiconductor die.

8. The integrated circuit of claim 7 , wherein the memory is a flash memory.

9. The integrated circuit of claim 7 , wherein the memory is an antifuse-based memory.

10. An integrated circuit comprising:

an array of flash memory cells organized into rows and columns, each cell in each row coupled to a row line and a column line;

a programming circuitry for erasing the array of flash memory cells, said programming circuitry implementing an method for reducing over-erase of the cells comprising:

following an initial erase of the array, selecting a row for an over-erase reducing operation;

concurrently applying an initial row programming voltage pulse to the row line, and an initial column programming voltage pulse to the column lines coupled to each cell in the selected row;

following the initial row and column programming voltage pulses, comparing an erased state of each of the cells in the selected row to a predetermined threshold; and

if the erased state of at least one of the cells in the selected row exceeds the predetermined threshold:

concurrently applying a next row programming voltage pulse to the row line and a next column programming voltage pulse to the column line coupled to each cell in the selected row whose erased state exceeds the predetermined threshold.

11. The integrated circuit of claim 10 , wherein the method further comprises:

programming selected ones of the flash memory cells to control the configuration of a programmable logic device.

12. The integrated circuit of claim 11 , wherein:

the programmable logic device is a field programmable gate array.

13. The integrated circuit of claim 10 , wherein the method further comprises:

concurrently applying a next row programming voltage pulse to the row line and a next column programming voltage pulse to the column line coupled to each cell in the selected row whose erased state exceeds the predetermined threshold includes:

applying an inhibit signal to the column line coupled to each cell whose erased state meets the predetermined threshold.

14. The integrated circuit of claim 10 , wherein the method further comprises:

cycling steps of:

comparing to the predetermined threshold, the erase state of each of the cells in the selected row whose erase state exceeded the predetermined threshold in a last compare; and

concurrently applying a next row programming voltage pulse to the row line and a next column programming voltage pulse to the column line coupled to each cell in the selected row whose erase state exceeded the predetermined threshold;

until at least one of the following conditions occurs:

the erased state of each cell in the selected row meets the predetermined threshold; and

the programming voltage pulse has reached a predetermined maximum.

15. The integrated circuit of claim 14 , wherein:

the predetermined maximum of the programming voltage pulse comprises at least one of: a maximum voltage, a maximum number of pulses; a maximum time period, and a maximum number of cycles.

16. The integrated circuit of claim 10 , wherein:

the flash cells are on the integrated circuit comprising a programmable logic device and

at least a portion of the flash cells are used to configure programmable logic of the programmable logic device.

17. The integrated circuit of claim 16 , wherein:

the programmable logic device is a field programmable gate array.