PLD providing soft wakeup logic
View Patent ↗A programmable logic device (PLD) with a plurality of programmable regions is disclosed. Some of the programmable regions have switch power or ground supplies to allow them to be put into a low-power state in one or more low-power modes. At least one of the programmable regions always remains on during the low-power modes to enable the user to design custom PLD power management logic that may be placed in the always-on programmable region.
1. A programmable logic integrated circuit device adapted to enter a low-power mode, the device comprising:
first and second voltage supply distribution lines each adapted to couple to an external voltage source;
a first transistor having a control terminal and first and second conductive terminals, the first conductive terminal coupled to the second supply distribution line;
a programmable logic device core coupled to the control circuit, and including a first region comprising a plurality of logic modules and having a first supply terminal coupled to the first supply distribution line, a second supply terminal coupled to the second supply distribution line, and a second region comprising a plurality of logic modules and having a third supply terminal coupled to the first supply distribution line and a fourth supply terminal coupled to the second conductive terminal of the transistor; and
a control circuit coupled to drive the control terminal of the first transistor, the control circuit further coupled to send at least one signal to the first region of the programmable logic device core and to receive at least one signal from the second region of the programmable logic device core.
2. The programmable logic integrated circuit device of claim 1 , wherein: the voltage potential applied to the first voltage supply distribution line is greater than the voltage potential applied to the second voltage supply distribution line.
3. The programmable logic integrated circuit device of claim 2 , wherein the voltage potential applied to the second voltage supply distribution line is ground.
4. The programmable logic integrated circuit device of claim 1 , wherein: the voltage potential applied to the second voltage supply distribution line is greater than the voltage potential applied to the first voltage supply distribution line.
5. The programmable logic integrated circuit device of claim 4 , wherein the voltage potential applied to the first voltage supply distribution line is ground.
6. The programmable logic integrated circuit device of claim 1 , further comprising: an external signal input line coupled to the control circuit and to the first region.
7. The programmable logic integrated circuit device of claim 6 , wherein the external signal input line is also coupled to the second region.
8. The programmable logic integrated circuit device of claim 6 , wherein:
the first region is adapted to remain active during a low-power mode; and
the second region is adapted to enter a low-power state during a low-power mode.
9. The programmable logic integrated circuit device of claim 1 , further comprising: a timer circuit coupled to the first region.
10. The programmable logic integrated circuit device of claim 1 , wherein the first and second regions are substantially physically adjacent.
11. The programmable logic integrated circuit device of claim 1 , wherein the first and second regions are substantially physically separated.
12. The programmable logic integrated circuit device of claim 1 , wherein the first region comprises a smaller number of logic modules than the second region.
13. The programmable logic integrated circuit device of claim 1 , wherein: the second region comprises a smaller number of logic modules than the first region.
14. The programmable logic integrated circuit device of claim 1 , wherein the construction of the second region is heterogeneous with respect to the construction of the first region.
15. The programmable logic integrated circuit device of claim 14 , wherein the voltage potential applied to the first voltage supply distribution line is greater than the voltage potential applied to the second voltage supply distribution line.
16. The programmable logic integrated circuit device of claim 15 , wherein the voltage potential applied to the second voltage supply distribution line is ground.
17. The programmable logic integrated circuit device of claim 14 , wherein the voltage potential applied to the second voltage supply distribution line is greater than the voltage potential applied to the first voltage supply distribution line.
18. The programmable logic integrated circuit device of claim 17 , wherein the voltage potential applied to the first voltage supply distribution line is ground.
19. The programmable logic integrated circuit device of claim 14 , further comprising an external signal input line coupled to the control circuit and to the first region.
20. The programmable logic integrated circuit device of claim 19 , wherein the external signal input line is also coupled to the second region.
21. The programmable logic integrated circuit device of claim 14 , further comprising: a timer circuit coupled to the programmable logic core.
22. The programmable logic integrated circuit device of claim 14 , wherein the first and second regions are substantially physically adjacent.
23. The programmable logic integrated circuit device of claim 14 , wherein the first and second regions are substantially physically separated.
24. The programmable logic integrated circuit device of claim 14 , wherein the first region comprises a smaller number of logic modules than the second region.
25. The programmable logic integrated circuit device of claim 14 , wherein the second region comprises a smaller number of logic modules than the first region.
26. The programmable logic integrated circuit device of claim 14 , wherein:
the first region is adapted to remain active during a low-power mode; and
the second region is adapted to enter a low-power state during a low-power mode.
27. The programmable logic integrated circuit device of claim 1 , wherein:
the first region is adapted to remain active during a low-power mode; and
the second region is adapted to enter a low-power state during a low-power mode.