Inverting flip-flop for use in field programmable gate arrays
View Patent ↗A flip-flop for use in a field programmable gate array integrated circuit device is disclosed. The flip-flop comprises a data output terminal coupled to a first programmable routing element, a data input terminal coupled to a second programmable routing element, and a clock input terminal, wherein a signal appearing at the data output terminal in response to a signal applied to the clock input terminal has the opposite logical polarity with respect to the corresponding logical signal applied to the data input terminal.
1. A circuit disposed in a programmable logic integrated circuit device, and coupled to a programmable logic routing fabric, the circuit comprising:
a logic function generator element including a plurality of data inputs and an output;
a first multiplexer having a first data input, a second data input, a control input, and an output, the output coupled to a first data input of the logic function generator element;
a second multiplexer having a first data input coupled to the output of the logic function generator element, a second data input coupled to the second data input of the first multiplexer, a control input, and an output;
a clocked data storage element having a clock input, a data input, and a data output, the data output coupled to the first data input of the first multiplexer; and
a third multiplexer having a non-inverting first data input coupled to the output of the clocked data storage element, an inverting second data input coupled to the output of the second multiplexer, a control input, and an output coupled to the data input of the clocked data storage element.
2. The circuit of claim 1 , further including a fourth multiplexer having a plurality of data inputs coupled to the programmable logic routing fabric, a control input, and an output coupled to the control input of the third multiplexer.
3. The circuit of claim 1 , further including a fifth multiplexer having a plurality of data inputs coupled to the programmable logic routing fabric, a control input, and an output coupled to the clock input of the clocked data storage element.
4. The circuit of claim 1 , further including a sixth multiplexer having a plurality of data inputs coupled to the programmable logic routing fabric, a control input, and an output coupled to the second data inputs of the first and second multiplexers.
5. The circuit of claim 4 , further including a seventh multiplexer having a plurality of data inputs coupled to the programmable logic routing fabric, a control input, and an output coupled to a third data input of the logic function generator.
6. The circuit of claim 5 , further including a eighth multiplexer having a plurality of data inputs coupled to the programmable logic routing fabric, a control input, and an output coupled to a fourth data input of the logic function generator.
7. The circuit of claim 1 wherein the function generator element is a lookup table.
8. The circuit of claim 1 wherein the clocked data storage element is a data flip-flop.
9. The circuit of claim 1 , further comprising a probe circuit coupled to the data output of the data flip-flop.
10. The circuit of claim 1 , further including:
a data output node coupled to the output of the logic function generator; and
a clocked data output node coupled to the data output of the clocked data storage element.
11. The circuit of claim 1 , further including a probe circuit having a probe input coupled to the output of the clocked data storage element and a probe output.
12. The circuit of claim 11 wherein the probe output is coupled to an I/O pad of the programmable logic integrated circuit device.
13. The circuit of claim 11 wherein the probe circuit includes:
a probe-enable switch coupled to the output of the clocked data storage element;
a probe control element;
a NOR gate having a first data input coupled to the probe control element, a second data input coupled to the probe-enable switch, and an output coupled to the probe output.
14. The circuit of claim 11 wherein the probe circuit includes:
a first transistor having a gate coupled to the output of the clocked data storage element, a source coupled to ground, and a drain;
a second transistor having a gate coupled to a source of a probe enable signal, a source coupled to the drain of the first transistor, and a drain;
a probe control element;
a NOR gate having a first data input coupled to the probe control element, a second data input coupled to the drain of the second transistor, and an output coupled to the probe output.
15. The circuit of claim 14 wherein:
the second data input of the NOR gate is coupled to the drain of the second transistor through a sense amplifier, and
the output of the NOR gate is coupled to an I/O pad of the programmable logic integrated circuit device through a buffer.