Non-volatile programmable memory cell for programmable logic array
A non-volatile programmable memory cell suitable for use in a programmable logic array includes a non-volatile MOS transistor of a first conductivity type in series with a volatile MOS transistor of a second conductivity type. The non-volatile MOS transistor may be a floating gate transistor, such as a flash transistor, or may be another type of non-volatile transistor such as a floating charge-trapping SONOS, MONOS transistor, or a nano-crystal transistor. A volatile MOS transistor, an inverter, or a buffer may be driven by coupling its gate or input to the common connection between the non-volatile MOS transistor and the volatile MOS transistor.
1. A non-volatile programmable memory cell comprising:
a non-volatile MOS transistor of a first conductivity type having a first source/drain connected to a first power supply potential, a second source/drain connected to an output node, a floating gate, and a control gate, the control gate connected to a non-volatile control gate node;
a volatile MOS transistor of a second conductivity type having a first source/drain connected to the output node, a second source/drain connected to a second power supply potential and a control gate connected to a volatile control gate node separate from the non-volatile control gate node; and
a volatile switch coupled to the output node through a resistor;
wherein an RC time constant of the memory cell is greater than a recovery time of the memory cell.
2. The non-volatile programmable memory cell of claim 1 wherein the volatile switch is a volatile MOS transistor having a gate coupled to the output node.
3. The non-volatile programmable memory cell of claim 1 wherein the volatile switch is a plurality of volatile MOS transistors of the same conductivity type each having a gate coupled to the output node.
4. The non-volatile programmable memory cell of claim 1 wherein the volatile switch is an inverter having an input coupled to the output node.
5. The non-volatile programmable memory cell of claim 1 wherein the volatile switch is a buffer having an input coupled to the output node.
6. The non-volatile programmable memory cell of claim 1 wherein the non-volatile MOS transistor is a floating gate transistor.
7. The non-volatile programmable memory cell of claim 1 wherein the non-volatile MOS transistor is a flash transistor.
8. The non-volatile programmable memory cell of claim 1 wherein the non-volatile MOS transistor is a charge-trapping transistor.
9. The non-volatile programmable memory cell of claim 1 wherein the non-volatile MOS transistor is a nano-crystal transistor.
10. The non-volatile programmable memory cell of claim 1 wherein the first conductivity type is N and the second conductivity type is P.
11. The non-volatile programmable memory cell of claim 1 wherein the first conductivity type is P and the second conductivity type is N.
12. The non-volatile programmable memory cell of claim 1 wherein the first conductivity type is N, the second conductivity type is P, and the volatile MOS transistor is N type.
13. The non-volatile programmable memory cell of claim 1 wherein the first conductivity type is P, the second conductivity type is N, and the volatile MOS transistor is N type.
14. The non-volatile programmable memory cell of claim 1 wherein the non-volatile MOS transistor has an active channel area defined in an active region disposed between two contacts, the active region in the active channel area having a width narrower than the width of the active region at the two contacts.
15. The non-volatile programmable memory cell of claim 14 wherein the width of the active region in the active channel area is about 0.12 microns and the width at of the active region at the two contacts is about 0.2 microns.
16. A non-volatile programmable memory cell comprising:
a non-volatile n-channel MOS pulldown transistor having a source connected to a first power supply potential, a drain connected to an output node, a floating gate and a control gate, the control gate coupled to a non-volatile gate node;
a volatile p-channel MOS pullup transistor having a source connected to a second power supply potential, a drain connected to the output node, and a control gate coupled to a volatile gate node separate from the non-volatile control gate node;
a volatile switch coupled to the output node through a resistor;
wherein an RC time constant of the memory cell is greater than a recovery time of the memory cell.
17. The non-volatile programmable memory cell of claim 16 wherein the volatile switch is a volatile n-charnel MOS transistor having a gate coupled to the output node.
18. The non-volatile programmable memory cell of claim 16 wherein the volatile switch is a plurality of volatile n-channel MOS transistors each having a gate coupled to the output node.
19. The non-volatile programmable memory cell of claim 16 wherein the volatile switch is an inverter having an coupled to the output node.
20. The non-volatile programmable memory cell of claim 16 wherein the volatile switch is a buffer having an input coupled to the output node.
21. The non-volatile programmable memory cell of claim 16 wherein the non-volatile n-channel MOS transistor is a floating gate transistor.
22. The non-volatile programmable memory cell of claim 16 wherein the non-volatile n-channel MOS transistor is a flash transistor.
23. The non-volatile programmable memory cell of claim 16 wherein the non-volatile n-channel MOS transistor is a floating charge-trapping transistor.
24. The non-volatile programmable memory cell of claim 16 wherein the non-volatile n-channel MOS transistor is a nano-crystal transistor.
25. The non-volatile programmable memory cell of claim 16 wherein the non-volatile MOS transistor has an active channel area defined in an active region disposed between two contacts, the active region in the active channel area having a width narrower than the width of the active region at the two contacts.
26. The non-volatile programmable memory cell of claim 25 wherein the width of the active region in the active channel area is about about 0.12 microns and the width at of the active region at the two contacts is about 0.2 microns.
27. A non-volatile programmable memory cell comprising:
a non-volatile p-channel MOS pullup transistor having a source connected to a first power supply potential, a drain connected to an output node, a floating gate, and a control gate, the control gate coupled to a non-volatile gate node;
a volatile n-channel MOS pulldown transistor having a source connected to a second power supply potential, a drain connected to the output node, and a control gate coupled to a volatile gate node separate from the non-volatile control gate node; and
a volatile switch coupled to the output node through a resistor;
wherein an RC time constant of the memory cell is greater than a recovery time of the memory cell.
28. The non-volatile programmable memory cell of claim 27 wherein the volatile switch is a volatile n-channel MOS transistor having a gate coupled to the output node.
29. The non-volatile programmable memory cell of claim 27 wherein the volatile switch is a plurality of volatile n-channel MOS transistors each having a gate coupled to the output node.
30. The non-volatile programmable memory cell of claim 27 wherein the volatile switch is an inverter having an input coupled to the output node.
31. The non-volatile programmable memory cell of claim 27 wherein the volatile switch is a buffer having an input coupled to the output node.
32. The non-volatile programmable memory cell of claim 27 wherein the non-volatile n-channel MOS transistor is a floating gate transistor.
33. The non-volatile programmable memory cell of claim 27 wherein the non-volatile n-channel MOS transistor is a flash transistor.
34. The non-volatile programmable memory cell of claim 27 wherein the non-volatile n-channel MOS transistor is a floating charge-trapping transistor.
35. The non-volatile programmable memory cell of claim 27 wherein the non-volatile n-channel MOS transistor is a nano-crystal transistor.
36. The non-volatile programmable memory cell of claim 27 wherein non-volatile MOS transistor has an active channel area defined in an active region disposed between two contacts, the active region in the active channel area having a width narrower than a the width of the active region at the two contacts.
37. The non-volatile programmable memory cell of claim 36 wherein the width of the active region in the active channel area is about about 0.12 microns and the width at of the active region at the two contacts is about 0.2 microns.