Reduced-edge radiation-tolerant non-volatile transistor memory cells
View Patent ↗An edgeless one-transistor flash memory array includes transistors that have two polysilicon gate layers that overlay an active region. The bottom polysilicon gate layer is electrically isolated. The memory is configured such that current passes from drain to source under the bottom polysilicon layer, such that it does not approach a field oxide region. An edgeless two-transistor programmable memory includes memory cells that have two active devices. Two polysilicon gate layers overlay two active regions and are shared between the two active devices. One of the devices is used to program and erase the cell while the other used as a programmable switch in a programmable logic device. The bottom polysilicon gate layer is electrically isolated. The memory is configured such that current passes from drain to source under the bottom polysilicon layer, such that it does not approach a field oxide region.
1. A reduced-edge flash transistor, comprising:
(a) an active region bounded by a shallow trench isolation region;
(b) a control gate overlaying a portion of the active region;
(c) a charge storage region disposed above the active region and aligned with and underneath the control gate for at least that portion of the control gate overlaying the active region;
(d) a conductively doped source region comprising a first portion of the active region that is not overlaid by the control gate and charge storage region; and
(e) a conductively doped drain region comprising a second portion of the active region that is not overlaid by the control gate and charge storage region, wherein:
(i) the source region and the drain region are positioned with respect to each other so that current passes from the drain region to the source region through a channel region underneath the charge storage region when the transistor is in the on state,
(ii) the current does not approach the shallow trench isolation region at edges of the channel region.
2. The reduced-edge flash transistor of claim 1 , wherein the drain region is laterally surrounded by the active region on all sides.
3. The reduced-edge flash transistor of claim 2 , wherein the charge storage region comprises a conductive material.
4. The reduced-edge flash transistor of claim 3 , wherein the conductive material comprises polysilicon.
5. The reduced-edge flash transistor of claim 2 , wherein the charge storage region comprises a non-conductive material.
6. The reduced-edge flash transistor of claim 5 , wherein the non-conductive material comprises SONOS.
7. The reduced-edge flash transistor of claim 5 , wherein the non-conductive material comprises silicon nanocrystals.
8. The reduced-edge flash transistor of claim 1 , wherein the widths of the control gate and the charge storage region are wider at the edge of the active region than they are over at least a portion of the remainder of the active region.
9. The reduced-edge flash transistor of claim 8 , wherein the charge storage region comprises a conductive material.
10. The reduced-edge flash transistor of claim 9 , wherein the conductive material comprises polysilicon.
11. The reduced-edge flash transistor of claim 8 , wherein the charge storage region comprises a non-conductive material.
12. The reduced-edge flash transistor of claim 11 , wherein the non-conductive material comprises SONOS.
13. The reduced-edge flash transistor of claim 11 , wherein the non-conductive material comprises silicon nanocrystals.
14. The reduced-edge flash transistor of claim 1 , wherein the source region and the drain region are each laterally surrounded by the active region on all sides.
15. The reduced-edge flash transistor of claim 14 , wherein:
(a) a conductive layer is disposed on top of the source and drain regions; and
(b) the source region and the drain region both remain electrically isolated from the surrounding active region.
16. The reduced-edge flash transistor of claim 15 , wherein the conductive layer comprises metal silicide.
17. The reduced-edge flash transistor of claim 1 , wherein the control gate and charge storage region are annular and surround the drain region, a distance between the source region and the drain region being shorter than a distance between the drain region and the shallow trench isolation region.