Programmable system on a chip for temperature monitoring and control
View Patent ↗A programmable system-on-a-chip integrated circuit device includes a programmable logic block, at least one user non-volatile memory block, and temperature sensing and control analog and digital circuits on a single semiconductor integrated circuit chip or a flip chip, face-to-face, or other multiple die configuration. The programmable system-on-a-chip integrated circuit with temperature measuring and control circuitry performs temperature measurement and control functions and can be used to create an on-chip temperature log.
1. A programmable system-on-a-chip integrated circuit device comprising:
a programmable logic block;
a digital input/output circuit block;
a non-volatile memory block;
a clock-generator circuit block;
an analog circuit block including an analog to digital converter and at least one temperature-sensing circuit coupled to an I/O pad and including a programmable voltage prescaling circuit;
an analog input/output circuit block; and
a programmable interconnect architecture including programmable elements and interconnect conductors, ones of the programmable elements coupled to the programmable logic block, the non-volatile memory block, the analog circuit block, the analog input/output circuit block, the digital input/output circuit block, and to the interconnect conductors, such that inputs and outputs of the programmable logic block, the non-volatile memory block, the analog circuit block, the analog input/output circuit block, and the digital input/output circuit block can be programmably coupled to one another.
2. The programmable system-on-a-chip integrated circuit device of claim 1 wherein:
the clock-generator circuit block is coupled to a phase locked loop having an output;
the programmable interconnect architecture includes at least one interconnect conductor coupled to the output of the clock-generator circuit; and
the programmable interconnect architecture includes at least one interconnect conductor coupled to the output of the phase locked loop by a programmable interconnect element.
3. The programmable system-on-a-chip integrated circuit device of claim 2 wherein the clock-generator circuit block includes a plurality of clock sources.
4. The programmable system-on-a-chip integrated circuit device of claim 3 wherein the clock-generator circuit block includes a clock source driven from an externally-connected crystal.
5. The programmable system-on-a-chip integrated circuit device of claim 3 wherein the clock-generator circuit block includes a clock source comprising an RC oscillator circuit.
6. The programmable system-on-a-chip integrated circuit device of claim 3 wherein the clock-generator circuit block includes an external clock signal input.
7. The programmable system-on-a-chip integrated circuit device of claim 3 , further including a glitchless clock multiplexer coupled to the outputs of the plurality of clock sources.
8. The programmable system-on-a-chip integrated circuit device of claim 6 , further including a glitchless clock multiplexer coupled to the outputs of the plurality of clock sources and to the external clock signal input.
9. The programmable system-on-a-chip integrated circuit device of claim 1 further including a static random-access memory block and wherein the programmable interconnect architecture is coupled to the static random-access memory block.
10. The programmable system-on-a-chip integrated circuit device of claim 9 wherein the static random-access memory block is configured into at least two sub-blocks.
11. The programmable system-on-a-chip integrated circuit device of claim 1 further including a microcontroller block and a static random-access memory block and wherein the programmable interconnect architecture is coupled to the microcontroller block and the static random-access memory block.
12. The programmable system-on-a-chip integrated circuit device of claim 9 wherein the static random-access memory block is configured into at least two sub-blocks.
13. The programmable system-on-a-chip integrated circuit device of claim 1 further including a microprocessor block and a static random-access memory block and wherein the programmable interconnect architecture is coupled to the microprocessor block and the static random-access memory block.
14. The programmable system-on-a-chip integrated circuit device of claim 13 wherein the static random-access memory block is configured into at least two sub-blocks.
15. The programmable system-on-a-chip integrated circuit device of claim 1 wherein the non-volatile memory block comprises flash memory.
16. The programmable system-on-a-chip integrated circuit device of claim 1 further including a digital input circuit coupled to the I/O pad.
17. The programmable system-on-a-chip integrated circuit device of claim 1 wherein the analog circuit block further includes at least one voltage-sensing circuit coupled to an I/O pad.
18. The programmable system-on-a-chip integrated circuit device of claim 17 wherein the at least one voltage-sensing circuit includes a programmable voltage prescaling circuit.
19. The programmable system-on-a-chip integrated circuit device of claim 17 further including a digital input circuit coupled to the I/O pad.
20. The programmable system-on-a-chip integrated circuit device of claim 1 wherein the analog circuit block further includes at least one current-sensing circuit coupled to a first I/O pad and a second I/O pad.
21. The programmable system-on-a-chip integrated circuit device of claim 20 wherein the at least one current-sensing circuit includes a programmable voltage prescaling circuit.
22. The programmable system-on-a-chip integrated circuit device of claim 20 further including a digital input circuit coupled to at least one of the first and second I/O pads.
23. The programmable system-on-a-chip integrated circuit device of claim 1 wherein the analog circuit block further includes at least one programmable MOSFET gate-drive circuit coupled to an I/O pad.
24. The programmable system-on-a-chip integrated circuit device of claim 1 wherein the analog circuit block further includes: at least one MOSFET gate-drive circuit coupled to a first I/O pad at least one voltage-sensing circuit coupled to a second I/O pad; and at least one current-sensing circuit coupled to the second I/O pad and a third I/O pad and wherein the at least one temperature-sensing circuit is coupled to a fourth I/O pad.
25. The programmable system-on-a-chip integrated circuit device of claim 17 further including a digital input circuit coupled to one of the second, third, and fourth I/O pads.
26. The programmable system-on-a-chip integrated circuit device of claim 1 wherein the non-volatile memory block has a first segment that may be programmably connected to a user-configured circuit and a second segment that may not be programmably connected to a user-configured circuit.
27. The programmable system-on-a-chip integrated circuit device of claim 1 further including a bandgap reference circuit.
28. The programmable system-on-a-chip integrated circuit device of claim 1 , further comprising a system controller block including a power-up controller configured to apply system power to the programmable logic block, the digital input/output circuit block, the non-volatile memory block, the analog circuit block, and the analog input/output circuit block in a predetermined sequence and a system supervisor block coupled to at least one of the programmable logic block, the digital input/output circuit block, the non-volatile memory block, the analog circuit block, and the analog input/output circuit block, and configured to monitor at least one function of at least one circuit external to the programmable system-on-a-chip integrated circuit device.
29. The programmable system-on-a-chip integrated circuit device of claim 28 wherein the system supervisor block is further configured to control at least one function of the at least one circuit external to the programmable system-on-a-chip integrated circuit device.