SRAM cell controlled by flash memory cell
First and second complimentary static random-access-memory cell bit lines are coupled to first and second bit nodes through first and second access transistors controlled by a word line. A first inverter has an input coupled to the first bit node and an output coupled to the second bit node. A second inverter has an input coupled to the second bit node and an output coupled to the first bit node through a first transistor switch. A transistor switch is coupled between the output of a non-volatile memory cell and the first bit node. A control circuit coupled to the gate of the transistor switch. Either the drive level of the non-volatile memory cell is selected to overpower the output of the second inverter or the second inverter is decoupled from the first bit node while the output of the non-volatile memory cell is coupled to the first bit node.
1. A multi-purpose static random-access-memory cell controllable by a non-volatile memory cell comprising:
a static random-access-memory cell coupled between first and second complimentary static random-access-memory cell bit nodes;
a static random-access-memory cell word line;
first and second complimentary static random-access-memory cell bit lines respectively coupled to the first and second complimentary static random-access-memory cell bit a first means for programming the static random-access-memory cell utilizing the static random-access-memory cell word line to selectively enable the first and second complementary static random-access-memory cell bit lines;
a configuration word line;
first and second complimentary configuration bit lines respectively coupled to the first and second complimentary static random-access-memory cell bit a second means for programming the static random-access-memory cell utilizing the configuration word line to selectively enable the first and second complimentary configuration bit lines;
a non-volatile memory clock line;
a third means for programming the static random-access-memory cell utilizing the non-volatile memory clock line to selectively enable programming the static random-access-memory cell to a value determined by an output of the non-volatile memory.
2. The multi-purpose static random-access-memory cell in claim 1 which further comprises:
a serial shift register stage having first and second complementary clock lines, said serial shift register stage coupled to the first and second complimentary static random-access-memory cell bit nodes.
3. The multi-purpose static random-access-memory cell in claim 1 wherein:
the first means for programming the static random-access-memory cell comprises:
a first transistor having a first node coupled to the first complimentary static random-access-memory cell bit line, a second node coupled to the first complimentary static random-access-memory cell bit node, and a gate coupled to and driven by the static random-access-memory cell word line; and
a second transistor having a first node coupled to the second complimentary static random-access-memory cell bit line, a second node coupled to the second complimentary static random-access-memory cell bit node, and a gate coupled to and driven by the static random-access-memory cell word line.
4. The multi-purpose static random-access-memory cell in claim 1 wherein:
the second means for programming the static random-access-memory cell comprises:
a first transistor having a first node coupled to the first complimentary configuration bit line, a second node coupled to the first complimentary static random-access-memory cell bit node, and a gate coupled to and driven by the static random-access-memory cell word line; and
a second transistor having a first node coupled to the second complimentary configuration bit line, a second node coupled to the second complimentary static random-access-memory cell bit node, and a gate coupled to and driven by the static random-access-memory cell word line.
5. The multi-purpose static random-access-memory cell in claim 1 wherein:
the third means for programming the static random-access-memory cell comprises:
a first transistor having a first node coupled to the output of the of the non-volatile memory cell, a second node coupled to the first complimentary static random-access-memory cell bit node, and a gate coupled to and driven by the non-volatile memory clock line;
a second transistor having a first node coupled ground, a second node, and a gate coupled to and driven by the output of the non-volatile memory cell; and
a third transistor having a first node coupled to the second node of the second transistor, a second node coupled to the second complimentary static random-access-memory cell bit node, and a gate coupled to and driven by the non-volatile memory clock line.
6. The multi-purpose static random-access-memory cell of claim 1 wherein:
the static random-access-memory cell comprises:
a first inverter having an input coupled to the first complimentary static random-access-memory cell bit node and an output coupled to the second complimentary static random-access-memory cell bit node; and
a second inverter having an input coupled to the second complimentary static random-access-memory cell bit node and an output coupled to the first complimentary static random-access-memory cell bit node.
7. The multi-purpose static random-access-memory cell of claim 6 wherein:
the output of the non-volatile memory cell has a drive level selected to overpower the output of the second inverter.
8. The multi-purpose static random-access-memory cell of claim 6 wherein:
the output of the non-volatile memory cell is buffered to overpower the output of the second inverter.
9. The multi-purpose static random-access-memory cell of claim 6 , further comprising:
a buffer having an input coupled to the second complimentary static random-access-memory cell bit node and an output coupleable to a circuit node to be controlled by the static random-access-memory cell.
10. The multi-purpose static random-access-memory cell of claim 1 , wherein:
the static random-access-memory cell comprises a programmable element for a programmable logic device.