Programmable system on a chip
View Patent ↗A programmable system-on-a-chip integrated circuit device comprises a programmable logic block, a non-volatile memory block, an analog sub-system, an analog input/output circuit block, and a digital input/output circuit block. A programmable interconnect architecture includes programmable elements and interconnect conductors. Ones of the programmable elements are coupled to the programmable logic block, the non-volatile memory block, the analog sub-system, the analog input/output circuit block, the digital input/output circuit block, and to the interconnect conductors, such that inputs and outputs of the programmable logic block, the non-volatile memory block, the analog sub-system, the analog input/output circuit block, and the digital input/output circuit block can be programmably coupled to one another.
1. A method of powering up a programmable system-on-a-chip including a V cc power input node, a bandgap reference circuit, a first voltage regulator circuit, a programmable logic circuit block coupled to an output of the first voltage regulator circuit, a second voltage regulator circuit, and an analog circuit block coupled to an output of the second voltage regulator circuit and including an analog-to-digital converter, the method comprising:
providing a V cc voltage potential to the V cc power input node;
determining whether the output of the bandgap reference circuit is outputting a predetermined bandgap voltage;
if the output of the bandgap reference circuit is outputting the predetermined bandgap voltage, determining whether the output of the first voltage regulator circuit has reached a predetermined threshold;
if the output of the first voltage regulator circuit has reached the predetermined threshold, determining whether the programmable logic block is functional;
if the programmable logic block is functional, initializing and configuring digital circuits of the programmable system-on-a-chip;
determining whether the output of the second voltage regulator circuit has reached a predetermined threshold;
if output of the second voltage regulator circuit has reached the predetermined threshold, calibrating the analog-to-digital converter.
2. The method of claim 1 wherein determining whether the output of the first voltage regulator circuit has reached a predetermined threshold comprises comparing the output of the first voltage regulator circuit to the bandgap voltage.
3. The method of claim wherein determining whether the output of the second voltage regulator circuit has reached a predetermined threshold comprises comparing the output of the second voltage regulator circuit to the bandgap voltage.
4. The method of claim 1 , further including determining whether the output of a reference voltage in the analog-to-digital converter is within a predetermined range prior to calibrating the analog-to-digital converter.
5. The method of claim 4 , wherein determining whether the output of the reference voltage in the analog-to-digital converter is within a predetermined range by comparing the bandgap voltage to the reference voltage in the analog-to-digital converter.
6. The method of claim 1 , wherein the system-on-a-chip further includes a non-volatile memory, and wherein the method further includes determining whether the non-volatile memory is functioning.
7. The method of claim 6 , wherein the system-on-a-chip further includes a non-volatile memory, and wherein the method further includes determining whether the non-volatile memory is functioning after determining whether the programmable logic block is functional.
8. The method of claim 1 , further including configuring a state machine in the programmable logic block after determining whether the programmable logic block is functional.
9. The method of claim 7 , further including configuring a state machine in the programmable logic block after determining whether the non-volatile memory is functional.
10. The method of claim 8 , wherein:
configuring the state machine in the programmable logic block includes configuring an analog-to-digital converter sequencer in the state machine; and then starting the analog-to-digital converter sequencer.
11. The method of claim 9 , wherein:
configuring the state machine in the programmable logic block includes configuring an analog-to-digital converter sequencer in the state machine; and then starting the analog-to-digital converter sequencer.
12. The method of claim 1 wherein determining whether the output of the bandgap reference circuit is outputting a predetermined bandgap voltage includes generating a bandgap-verified signal after determining that the output of the bandgap reference circuit is outputting the predetermined bandgap voltage.
13. The method of claim 12 , wherein determining whether the output of the first voltage regulator circuit has reached a predetermined threshold is performed in response to the bandgap-verified signal.
14. The method of claim 1 , wherein determining whether the output of the first voltage regulator circuit has reached a predetermined threshold further includes generating a first-voltage-regulator-circuit-verified signal after determining that the first voltage regulator circuit has reached the predetermined threshold.
15. The method of claim 14 , wherein determining whether the programmable logic block is functional is performed in response to the first-voltage-regulator-circuit-verified signal.
16. The method of claim 1 wherein determining whether the programmable logic block is functional further includes generating a programmable-logic-verified signal after determining that the programmable logic block is functional.
17. The method of claim 1 , wherein initializing and configuring digital circuits of the programmable system-on-a-chip further includes generating a digital-circuits-configured signal after initializing and configuring digital circuits of the programmable system-on-a-chip.
18. The method of claim 17 , wherein initializing and configuring digital circuits of the programmable system-on-a-chip is performed in response to the first-voltage-regulator-circuit-verified signal.
19. The method of claim 1 , wherein determining whether the output of the second voltage regulator circuit has reached a predetermined threshold further includes generating a second-voltage-regulator-circuit-verified signal after determining that the second voltage regulator circuit has reached the predetermined threshold.
20. The method of claim 19 , wherein calibrating the analog-to-digital converter is performed in response to the second-voltage-regulator-circuit-verified signal.
21. The method of claim 6 , wherein determining whether the non-volatile memory is functional further includes generating a non-volatile-memory-functional signal after determining that the non-volatile memory is functional.
22. The method of claim 21 wherein configuring a state machine in the programmable logic block is performed in response to the non-volatile-memory-functional signal.
23. The method of claim 1 , further including:
providing a system supervisor circuit after determining that the output of the bandgap reference circuit is outputting the predetermined bandgap voltage;
communicating a first signal to the system supervisor circuit;
communicating a second signal to the system supervisor circuit after determining that the output of the first voltage regulator circuit has reached the predetermined threshold;
communicating a third signal to the system supervisor circuit after determining that the programmable logic block is functional;
communicating a fourth signal to the system supervisor circuit after determining that the digital circuits of the programmable system-on-a-chip have been initialized and configured;
communicating a fifth signal to the system supervisor circuit after determining that the output of the second voltage regulator circuit has reached the predetermined threshold;
communicating a sixth signal to the system supervisor circuit after determining that the analog-to-digital converter has been calibrated; and
sending at least one control signal from the system supervisor circuit to off-chip devices in response to the first through sixth signals.
24. The method of claim 23 wherein the at least one control signal includes at least one off-chip device power-up sequence signal.
25. The method of claim 23 wherein the at least one control signal includes at least one system clock enable signal.
26. The method of claim 23 wherein the at least one control signal includes at least one system reset signal.