Field-programmable gate array low voltage differential signaling driver utilizing two complimentary output buffers
View Patent ↗A low voltage signaling differential signaling driver comprising a first output line coupled to a delay circuit, a first multiplexer and a first output buffer. The first output line is also coupled to an inverter, a second multiplexer and a second output buffer.
1. A field programmable gate array comprising:
a low voltage signaling driver circuit having a first input line, a second input line, a first output line, and a second output line comprising:
a first output buffer having an input and an output connected to the first output line;
a second output buffer having an input and an output connected to the second output line;
a delay circuit responsively connected to said first input line;
an inverter responsively connected to said first input line;
a first multiplexer having a first input connected to an output of said delay circuit, a second input connected to said first input line, a selector, and an output connected to the input of said first output buffer; and
a second multiplexer having a first input connected to an output of said inverter, a second input connected to said second input line, a selector, and an output connected to the input of said second output buffer;
and
programmable elements coupled to the selectors of and providing signals to control the first multiplexer and the second multiplexer.
2. The field programmable gate array in claim 1 wherein:
the low voltage signaling driver circuit further comprises:
control circuitry connected to said first multiplexer and to said second multiplexer to determine a signal connected to said first output buffer and a signal connected to said second output buffer by said second multiplexer.
3. The field programmable gate array in claim 2 wherein:
said control circuitry signals said first multiplexer to connect said delay circuit to said first output buffer and said second multiplexer to connect said inverter of said first output signal said second output buffer to provide low voltage differential signaling.
4. The field programmable gate array in claim 2 wherein:
said control circuitry signals said first multiplexer to connect first output line to said first output buffer and said second multiplexer to connect said second output line to said second output buffer to allow said first input buffer and said second input buffer to operate independently.
5. The field programmable gate array in claim 1 wherein:
the low voltage signaling driver circuit further comprises:
a first output pad connected to the first output line; and
a second output pad connected to the second output line.
6. The field programmable gate array in claim 1 wherein:
the inverter is programmably coupled to the first input line utilizing a programmable element.