Enhanced field programmable gate array
An enhanced performance field programmable gate array integrated circuit comprises a field programmable gate array and other functional circuitry such as a mask-programmable gate array in the same integrated circuit. A circuit interface provides communication between the field programmable gate array, the mask-programmable gate array and the integrated circuit I/O.
1. An integrated circuit device comprising:
a field programmable gate array region having: an input line, an output line, and an enable line;
a mask-programmable gate array region having: an input line, an output line, and an enable line;
an I/O system including I/O pads and associated driver circuits having: an input line, and output line, and an enable line; and
a user-programmable interconnect architecture for selectively making connections between and coupled to the input line, the output line, and the enable line for said field programmable gate array region, said mask-programmable gate array region, and said I/O system, wherein:
the user-programmable interconnect architecture comprises:
a first multiplexer having:
a first data input responsively coupled to the enable signal line of the field programmable gate array region;
a second data input responsively coupled to the enable signal line of the mask-programmable gate array region;
an output coupled to the enable signal line for the I/O system; and
a select input.
2. The integrated circuit device in claim 1 wherein:
the user-programmable interconnect architecture comprises:
a second multiplexer having:
a first data input responsively coupled to the output signal line of the field programmable gate array region;
a second data input responsively coupled to the output signal line of the mask-programmable gate array region;
an output coupled to the output signal line for the I/O system; and
a select input.
3. The integrated circuit device in claim 1 wherein:
the user-programmable interconnect architecture comprises:
a third multiplexer having:
a first data input responsively coupled to the input signal line of the I/O system;
a second data input responsively coupled to the output signal line of the mask-programmable gate array region;
an output coupled to the output signal line for the field programmable gate array region; and
a select input.
4. The integrated circuit device in claim 3 wherein:
the user-programmable interconnect architecture further comprises:
a fifth multiplexer having:
a first data input responsively coupled to the enable signal line of the I/O system;
a second data input;
an output coupled to the enable for the third multiplexer; and
a select input.
5. The integrated circuit device in claim 3 wherein:
the integrated circuit device further comprises:
a second programmable element coupled to and controlling the enable of the third multiplexer; and
a third programmable element coupled to and controlling the second data input of the third multiplexer.
6. The integrated circuit device in claim 1 wherein:
the user-programmable interconnect architecture comprises:
a fourth multiplexer having:
a first data input responsively coupled to the input signal line of the I/O
system;
a second data input responsively coupled to the output signal line of the field programmable gate array region;
an output coupled to the output signal line for the mask-programmable gate array region; and
a select input.
7. The integrated circuit device in claim 6 wherein:
the user-programmable interconnect architecture further comprises:
a sixth multiplexer having:
a first data input responsively coupled to the enable signal line of the I/O system;
a second input; and
an output coupled to the enable for the fourth multiplexer; and
a select input.
8. The integrated circuit device in claim 7 wherein:
the integrated circuit device further comprises:
a fourth programmable element coupled to and controlling the enable of the fourth multiplexer; and
a fifth programmable element coupled to and controlling the second data input of the fourth multiplexer.
9. The integrated circuit device in claim 1 wherein:
the user-programmable interconnect architecture further comprises:
a first control line, a second control line, a third control line, a fourth control line, and fifth control line;
a first multiplexer having:
a first data input responsively coupled to the enable signal line of the field programmable gate array region;
a second data input responsively coupled to the enable signal line of the mask-programmable gate array region and
an output coupled to the enable signal line for the I/O system; and
a select input responsively coupled to the first control line;
a second multiplexer having:
a first data input responsively coupled to the output signal line of the field programmable gate array region;
a second data input responsively coupled to the output signal line of the mask-programmable gate array region; and
an output coupled to the output signal line for the I/O system; and
a select input responsively coupled to the first control line;
a fifth multiplexer having:
a first data input responsively coupled to the enable signal line of the I/O system;
a second input responsively coupled to the third control line; and
an output; and
a select input responsively coupled to the second control line;
a sixth multiplexer having:
a first data input responsively coupled to the enable signal line of the I/O system;
a second data input responsively coupled to the fourth control line; and
an output; and
a select input responsively coupled to the firth control line;
a third multiplexer having:
a first data input responsively coupled to the input signal line of the I/O system;
a second data input responsively coupled to the output signal line of the mask-programmable gate array region; and
an output coupled to the output signal line for the field programmable gate array region; and
a select input responsively coupled to the output of the fifth multiplexer;
a fourth multiplexer having:
a first data input responsively coupled to the input signal line of the I/O system; and
a second data input responsively coupled to the output signal line of the field programmable gate array region;
an output coupled to the output signal line for the mask-programmable gate array region; and
a select input responsively coupled to the output of the sixth multiplexer.
10. The integrated circuit device in claim 9 wherein:
the integrated circuit device further comprises:
a first programmable element coupled to the first control line;
a second programmable element coupled to the second control line;
a third programmable element coupled to the third control line;
a fourth programmable element coupled to the fourth control line; and
a fifth programmable element coupled to the fifth control line.
11. The integrated circuit device in claim 9 wherein:
the I/O system comprises:
a first buffer having an input responsively coupled to an I/O pad and an output coupled to the input line for the I/O system;
a second buffer having an input coupled to the output line of the I/O system, and output coupled to the I/O pad and an enable coupled to the enable line of the I/O system.
12. An integrated circuit device comprising:
a field programmable gate array region having: an input line, an output line, and an enable line;
an analog circuit block;
an I/O system including I/O pads and associated driver circuits having: an input line, and output line, and an enable line; and
a user-programmable interconnect architecture for selectively making connections between and coupled to the input line, the output line, and the enable line for said field programmable gate array region, region analog circuit block, and said I/O system, wherein:
the user-programmable interconnect architecture comprises:
a multiplexer having:
a first data input responsively coupled to the enable signal line of the field programmable gate array region;
a second data input responsively coupled to the analog circuit block;
an output coupled to the enable signal line for the I/O system; and
a select input.
13. The integrated circuit device of claim 12 , wherein:
the analog circuit block comprises at least one of an A/D circuit and a D/A circuit.
14. An integrated circuit device comprising:
a field programmable gate array region having: an input line, an output line, and an enable line;
an ALU specialized digital circuit block;
an I/O system including I/O pads and associated driver circuits having: an input line, and output line, and an enable line; and
a user-programmable interconnect architecture for selectively making connections between and coupled to the input line, the output line, and the enable line for said field programmable gate array region, said ALU specialized digital circuit block, and said I/O system, wherein:
the user-programmable interconnect architecture comprises:
a multiplexer having:
a first data input responsively coupled to the enable signal line of the field programmable gate array region;
a second data input responsively coupled to the ALU specialized digital circuit block;
an output coupled to the enable signal line for the I/O system; and
a select input.
15. An integrated circuit device comprising:
a field programmable gate array region having: an input line, an output line, and an enable line;
a DSP specialized digital circuit block;
an I/O system including I/O pads and associated driver circuits having: an input line, and output line, and an enable line; and
a user-programmable interconnect architecture for selectively making connections between and coupled to the input line, the output line, and the enable line for said field programmable gate array region, said DSP specialized digital circuit block, and said I/O system, wherein:
the user-programmable interconnect architecture comprises:
a multiplexer having:
a first data input responsively coupled to the enable signal line of the field programmable gate array region;
a second data input responsively coupled to the DSP specialized digital circuit block;
an output coupled to the enable signal line for the I/O system; and
a select input.
16. An integrated circuit device comprising:
a field programmable gate array region having: an input line, an output line, and an enable line;
a high speed serial connection specialized I/O function circuit block;
an I/O system including I/O pads and associated driver circuits having: an input line, and output line, and an enable line; and
a user-programmable interconnect architecture for selectively making connections between and coupled to the input line, the output line, and the enable line for said field programmable gate array region, said high speed serial connection specialized I/O function circuit block, and said I/O system, wherein:
the user-programmable interconnect architecture comprises:
a multiplexer having:
a first data input responsively coupled to the enable signal line of the field programmable gate array region;
a second data input responsively coupled to the high speed serial connection specialized I/O function circuit block;
an output coupled to the enable signal line for the I/O system; and
a select input.