IP Library Granted Patent US 8,110,888
Granted Patent B2
US 8,110,888 · App. 12/206,954 · Granted Feb 7, 2012

Edge termination for high voltage semiconductor device

Assignee: Microsemi Corporation
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Quick Facts
Patent No.
US 8,110,888
App. No.
12/206,954
Granted
Feb 7, 2012
Kind
B2
Abstract

High voltage semiconductor devices with high-voltage termination structures are constructed on lightly doped substrates. Lightly doped p-type substrates are particularly prone to depletion and inversion from positive charges, degrading the ability of associated termination structures to block high voltages. To improve the efficiency and stability of termination structures, second termination regions of the same dopant type as the substrate, more heavily doped than the substrate but more lightly doped than first termination regions, are positioned adjoining the first termination regions. The second termination regions raise the field threshold voltage where the surface is vulnerable and render the termination structure substantially insensitive to positive charges at the surface. The use of higher dopant concentration in the gap region without causing premature avalanche is facilitated by only creating second termination regions for regions lacking field plate protection.

Claims (39)

1. A semiconductor device comprising a lightly-doped substrate of a first semiconductor type, a central active area formed in the substrate, and a high-voltage termination structure surrounding the central active area, wherein the high-voltage termination structure further comprises:

a plurality of first termination regions of a second semiconductor type extending to a first depth beneath an upper surface of the substrate;

a plurality of first spans of the substrate laterally separating the first termination regions;

a plurality of discrete field oxide regions substantially covering the first spans of the substrate;

a plurality of second spans of the substrate above the first termination regions laterally separating the discrete field oxide regions;

at least one second termination region of the first semiconductor type subjacent each first span of the substrate, the second termination region adjoining and forming a p-n junction with one of the first termination regions on a side of the respective first termination region nearest to the central active region, extending to a second depth from the surface of the substrate less than the first depth; and

a plurality of field plates, each field plate covering a portion of each respective field oxide region closest to the central active area, the field plates being laterally separated by gap regions of the substrate;

each field plate having a first end overlying and capacitively or resistively coupled to the respective first termination region and a second end overlying a portion of the respective discrete field oxide region nearest to the central active area, so that the field plate and field plate ends are spaced laterally away from the p-n junction;

the dopant concentration in the second termination regions being light enough to avoid premature avalanche in the depletion region and heavy enough to counteract the field effect from positive charges above the oxide-semiconductor interface.

2. A semiconductor device according to claim 1 wherein the dopant dose in the second termination regions ranges from about 4.0E11 cm −2 to about 4E12 cm −2 .

3. A semiconductor device according to claim 1 wherein a plurality of second termination regions of the first semiconductor type adjoin and form a plurality of p-n junctions with both the first termination regions of the second semiconductor type underlying the portions of the field oxide regions furthest from the central active area and the first termination regions of the second semiconductor type underlying the portions of the field oxide regions closest to the central active area.

4. A semiconductor device according to claim 1 wherein the second termination region is contiguously doped at the surface of the substrate.

5. A semiconductor device according to claim 4 wherein the dopant dose in the second termination regions ranges from about 5.0E10 cm −2 to about 5.0E11 cm −2 .

6. A semiconductor device according to claim 4 wherein the dopant dose in the second termination regions ranges from about 2.0E10 cm −2 to about 1.0E11 cm −2 .

7. A semiconductor device according to claim 1 , wherein the second termination region is selectively doped subjacent a first portion of the span of the substrate adjoining the side of the first termination region closest to the active device area and forming the p-n junction while leaving a second portion of the span of the substrate lightly doped.

8. A semiconductor device comprising a lightly-doped p-type substrate, a central active area formed in the substrate, and a high-voltage termination structure surrounding the central active area, wherein the high-voltage termination structure further comprises:

a plurality of n-type first termination regions extending to a first depth beneath an upper surface of the substrate;

a plurality of first spans of the substrate laterally separating the first termination regions;

a plurality of discrete field oxide regions substantially covering the first spans of the substrate;

a plurality of second spans of the substrate above the first termination regions separating the discrete field oxide regions;

at least one p-type second termination region subjacent each first span of the substrate, the second termination region adjoining and forming a p-n junction with one of the first termination regions on a side of the respective first termination region nearest to the central active region, extending to a second depth from the surface of the substrate less than the first depth, having a dopant concentration higher than the dopant concentration of the substrate and lower than the dopant concentration of first termination regions; and

a plurality of field plates, each field plate covering a portion of each respective field oxide region closest to the central active area, the field plates being laterally separated by gap regions of the substrate;

each field plate having a first end overlying and capacitively or resistively coupled to the respective first termination region and a second end overlying a portion of the discrete field oxide region nearest to the central active area, so that the field plate and field plate ends are spaced laterally away from the p-n junction;

the dopant concentration in the second termination region being light enough to avoid premature avalanche in the depletion region and heavy enough to counteract the field effect from positive charges above the oxide-semiconductor interface.

9. A semiconductor device according to claim 8 wherein the p-type dopant dose in the second termination regions ranges from about 4.0E11 cm −2 to about 4E12 cm −2 .

10. A semiconductor device according to claim 8 wherein a plurality of p-type second termination regions adjoin and form a plurality of p-n junctions with both the n-type first termination regions underlying the portions of the field oxide regions furthest from the central active area and the n-type first termination regions underlying the portions of the field oxide regions closest to the central active area.

11. A semiconductor device according to claim 8 wherein the second termination region is contiguously doped at the surface of the substrate.

12. A semiconductor device according to claim 8 , wherein the second termination region is selectively doped subjacent a first portion of the span of the substrate adjoining the side of the first termination region closest to the active device area and forming the p-n junction while leaving a second portion of the span of the substrate lightly doped.

13. A method of fabricating a semiconductor device having a central active area and a high-voltage termination structure surrounding the central active area on a lightly-doped substrate of a first semiconductor type, the method comprising:

forming a plurality of first termination regions of a second semiconductor type extending to a first depth beneath an upper surface of the substrate and separated by a plurality of first spans of the substrate;

forming a plurality of discrete field oxide regions substantially covering the first spans of the substrate and separated laterally by second spans of the substrate above the first termination regions;

forming at least one second termination region of the first semiconductor type subjacent each span of the substrate, the second termination region adjoining and forming a p-n junction with one of the first termination regions on a side of the respective first termination region nearest to the central active region, extending to a second depth from the surface of the substrate less than the first depth; and

forming a plurality of field plates, each covering a portion of each respective field oxide region closest to the central active area, the field plates being laterally separated by gap regions of the substrate;

each field plate having a first end overlying and capacitively or resistively coupled to the respective first termination region and a second end overlying a portion of the discrete field oxide region nearest to the central active area, so that the field plate and field plate ends are spaced laterally away from the p-n junction;

the dopant concentration in the second termination region being light enough to avoid premature avalanche in the depletion region and heavy enough to counteract the field effect from positive charges above the oxide-semiconductor interface.

14. A method of fabricating a semiconductor device according to claim 13 wherein the forming of the second termination regions of the first semiconductor type includes doping the second termination regions at a dopant dose from about 4.0E11 cm −2 to about 4E12 cm −2 .

15. A method of fabricating a semiconductor device according to claim 13 , wherein the second termination region is selectively doped subjacent a first portion of the span of the substrate adjoining the side of the first termination region closest to the active device area and forming the p-n junction while leaving a second portion of the span of the substrate lightly doped.

16. A method of fabricating a semiconductor device according to claim 13 , wherein the second termination region is selectively doped subjacent a first portion of the span of the substrate adjoining the side of the first termination region closest to the active device area and forming the p-n junction while leaving a second portion of the span of the substrate lightly doped wherein the first semiconductor type is p-type.

17. A method of fabricating a semiconductor device according to claim 13 , wherein the first semiconductor type is p-type and the second semiconductor type is n-type.

Assignments (10)
RELEASE OF SECURITY INTEREST Recorded Mar 9, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059358/0001 →
RELEASE OF SECURITY INTEREST Recorded Feb 25, 2022
From: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059333/0222 →
SECURITY INTEREST Recorded Sep 18, 2018
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
Reel/Frame 047103/0206 →
SECURITY INTEREST Recorded Jun 25, 2018
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 046426/0001 →
RELEASE OF SECURITY INTEREST Recorded May 29, 2018
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: MICROSEMI CORPORATION; MICROSEMI SEMICONDUCTOR (U.S.), INC.; MICROSEMI FREQUENCY AND TIME CORPORATION; MICROSEMI COMMUNICATIONS, INC.; MICROSEMI SOC CORP.; MICROSEMI CORP. - POWER PRODUCTS GROUP; MICROSEMI CORP. - RF INTEGRATED SOLUTIONS
Reel/Frame 046251/0391 →
PATENT SECURITY AGREEMENT Recorded Feb 3, 2016
From: MICROSEMI CORPORATION; MICROSEMI SEMICONDUCTOR (U.S.) INC. (F/K/A LEGERITY, INC., ZARLINK SEMICONDUCTOR (V.N.) INC., CENTELLAX, INC., AND ZARLINK SEMICONDUCTOR (U.S.) INC.); MICROSEMI FREQUENCY AND TIME CORPORATION (F/K/A SYMMETRICON, INC.); MICROSEMI COMMUNICATIONS, INC. (F/K/A VITESSE SEMICONDUCTOR CORPORATION); MICROSEMI SOC CORP. (F/K/A ACTEL CORPORATION); MICROSEMI CORP. - POWER PRODUCTS GROUP (F/K/A ADVANCED POWER TECHNOLOGY INC.); MICROSEMI CORP. - RF INTEGRATED SOLUTIONS (F/K/A AML COMMUNICATIONS, INC.)
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 037691/0697 →
RELEASE OF SECURITY INTEREST Recorded Jan 19, 2016
From: BANK OF AMERICA, N.A.
To: MICROSEMI CORPORATION; MICROSEMI CORP.-ANALOG MIXED SIGNAL GROUP, A DELAWARE CORPORATION; MICROSEMI SOC CORP., A CALIFORNIA CORPORATION; MICROSEMI SEMICONDUCTOR (U.S.) INC., A DELAWARE CORPORATION; MICROSEMI FREQUENCY AND TIME CORPORATION, A DELAWARE CORPORATION; MICROSEMI COMMUNICATIONS, INC. (F/K/A VITESSE SEMICONDUCTOR CORPORATION), A DELAWARE CORPORATION; MICROSEMI CORP.-MEMORY AND STORAGE SOLUTIONS (F/K/A WHITE ELECTRONIC DESIGNS CORPORATION), AN INDIANA CORPORATION
Reel/Frame 037558/0711 →
NOTICE OF SUCCESSION OF AGENCY Recorded Apr 9, 2015
From: ROYAL BANK OF CANADA (AS SUCCESSOR TO MORGAN STANLEY & CO. LLC)
To: BANK OF AMERICA, N.A., AS SUCCESSOR AGENT
Reel/Frame 035657/0223 →
PATENT SECURITY AGREEMENT Recorded Feb 11, 2011
From: WHITE ELECTRONIC DESIGNS CORP.; ACTEL CORPORATION; MICROSEMI CORPORATION
To: MORGAN STANLEY & CO. INCORPORATED
Reel/Frame 025783/0613 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 9, 2008
From: ZHANG, JINSHU; SDRULLA, DUMITRU; TSANG, DAH WEN
To: MICROSEMI CORPORATION
Reel/Frame 021500/0417 →
Continuity (2)
Provisional Application 60973345 · Sep 18, 2007
Related Publication 20090072340A1 · Mar 19, 2009