Charge trap-type 3-level non-volatile semiconductor memory device and method of driving the same

1. A non-volatile semiconductor memory device, comprising:

a memory array including a plurality of memory elements each capable of storing data in at least two charge trap regions depending on a direction of current flow;

a page buffer driven to map three data bits to threshold voltage groups of the two charge trap regions; and

a row decoder for controlling a word line of a selected memory element of the memory array.

2. The non-volatile semiconductor memory device according to claim 1 , wherein the two charge trap regions are formed in a single memory element.

3. The non-volatile semiconductor memory device according to claim 1 , wherein the page buffer comprises:

a transmission node capable of providing data to the memory array;

a sensing node capable of sensing data from the memory array;

a first latch block capable of storing first latch data and mapping the first latch data to the transmission node, the first latch block selectively flopping the first latch data depending on a voltage level of the sensing node; and

a second latch block capable of storing second latch data and mapping the second latch data to the transmission node, the second latch block selectively flopping the second latch data depending on the voltage level of the sensing node,

wherein the first latch data inversely flops depending on the voltage level of the sensing node and a logic state of the second latch data.

4. The non-volatile semiconductor memory device according to claim 3 , wherein the first latch block comprises:

a first latch unit for storing the first latch data and mapping the first latch data to the transmission node in response to a first block selection signal;

a first flop unit driven to change the first latch data from a first logic state to a second logic state; and

an inverting flop unit driven to change the first latch data from the second logic state to the first logic state.

5. The non-volatile semiconductor memory device according to claim 4 , wherein the first flop unit comprises:

transmission means driven to change the first latch data from the first logic state to the second logic state depending on the logic state of the second latch data; and

flop means driven to change the first latch data from the first logic state to the second logic state depending on the voltage level of the sensing node.

6. The non-volatile semiconductor memory device according to claim 4 , wherein the inverting flop unit flops the first latch data from the second logic state to the first logic state depending on the voltage level of the sensing node, the flop of the first latch data being interrupted depending on the logic state of the second latch data.

7. The non-volatile semiconductor memory device according to claim 4 , wherein the second latch block comprises:

a second latch unit for storing the second latch data, and mapping the second latch data to the transmission node in response to a second block selection signal; and

a second flop unit driven to change the second latch data from a first logic state to a second logic state.

8. The non-volatile semiconductor memory device according to claim 1 , wherein the non-volatile semiconductor memory device is a NOR-type memory device.

9. The non-volatile semiconductor memory device according to claim 1 , wherein the non-volatile semiconductor memory device is a NAND-type memory device.

10. A programming method for a non-volatile semiconductor memory device including a plurality of memory elements, each capable of storing data in at least two charge trap regions, the programming method programming three data bits in the first and second charge trap regions, the first and second charge trap regions each having a threshold voltage that belongs to first to third threshold voltage groups having sequentially increasing threshold voltages, the programming method comprising:

programming a first bit by programming the threshold voltage of at least one of the first and second charge trap regions in response to a state of the first data bit;

programming a second bit by programming the threshold voltage of at least one of the first and second charge trap regions in response to a state of the second data bit and a result of programming the first bit; and

programming a third bit by programming the threshold voltage of at least one of the first and second charge trap regions in response to a state of the third data bit and a result of programming the second bit.

11. The programming method according to claim 10 , wherein:

programming the first bit includes programming the first charge trap region to the second threshold voltage group in response to the state of the first data bit,

programming the second bit includes programming a threshold voltage of any one of the first and second charge trap regions to the third threshold voltage group in response to the state of the second data bit, the charge trap region to be programmed to the third threshold voltage group being selected based on results of programming the first bit, and

programming the third bit includes programming a threshold voltage of any one of the first and second charge trap regions to the second threshold voltage group in response to the state of the third data bit, the charge trap region to be programmed to the second threshold voltage group being selected based on results of programming the second bit.

12. The programming method according to claim 11 , wherein the non-volatile semiconductor memory device comprises a first latch unit for storing first latch data to program the first charge trap region, and a second latch unit for storing second latch data to program the second charge trap region.

13. The programming method according to claim 12 , wherein programming the second bit comprises:

controlling the first and second latch data using the second data bit;

controlling the second latch data, using data programmed in the first charge trap region;

controlling the first latch data, using the controlled second latch data; and

controlling threshold voltages of the first and second charge trap regions using the controlled first and second latch data.

14. The programming method according to claim 12 , wherein programming the third bit comprises:

controlling the first and second latch data using the third data bit;

controlling the second latch data, using data programmed in the second charge trap region;

controlling the first latch data, using the second latch data controlled using the data programmed in the second charge trap region; and

controlling threshold voltages of the first and second charge trap regions using the controlled first and second latch data.

15. The programming method according to claim 10 , wherein the non-volatile semiconductor memory device is a NOR-type memory device.

16. The programming method according to claim 10 , wherein the non-volatile semiconductor memory device is a NAND-type memory device.

17. A reading method for a non-volatile semiconductor memory device including a plurality of memory elements, each capable of storing data in at least two charge trap regions depending on a direction of current flow, the reading method reading three data bits stored in the first and second charge trap regions, the first and second charge trap regions each having a threshold voltage that belongs to first to third threshold voltage groups having sequentially increasing threshold voltages, the reading method comprising:

reading a first data bit by determining the threshold voltage group of the threshold voltage of the first charge trap region and by determining the threshold voltage group of the threshold voltage of the second charge trap region;

reading a second data bit by determining the threshold voltage group of the threshold voltage of the first charge trap region and by determining the threshold voltage group of the threshold voltage of the second charge trap region; and

reading a third data bit by determining the threshold voltage group of the threshold voltage of the first charge trap region and by determining the threshold voltage group of the threshold voltage of the second charge trap region.

18. The reading method according to claim 17 , wherein:

reading the first data bit includes verifying the threshold voltage in the first threshold voltage group of the first charge trap region and the threshold voltage in the third threshold voltage group of the second charge trap region,

reading the second data bit includes verifying the threshold voltage in the third threshold voltage group of the first and second charge trap regions, and

reading the third data bit includes verifying the threshold voltage in the second threshold voltage group of the first charge trap region and the threshold voltage in the first and third threshold voltage groups of the second charge trap region.

19. The reading method according to claim 18 , wherein the non-volatile semiconductor memory device comprises a first latch unit for storing first latch data to program the first charge trap region, and a second latch unit for storing second latch data to program the second charge trap region.

20. The reading method according to claim 19 , wherein reading the first data bit comprises:

setting the first and second latch data;

flopping the second latch data, using data depending on the threshold voltage of the first charge trap region which is verified based on a first reference voltage between the first and second threshold voltage groups;

controlling the first latch data using the second latch;

flopping the first latch data, using data depending on the threshold voltage of the second charge trap region, which is verified based on a second reference voltage between the second and third threshold voltage groups; and

verifying the first latch data.

21. The reading method according to claim 19 , wherein reading the second data bit comprises:

setting the first and second latch data;

controlling the second latch data, using data depending on the threshold voltage of the second charge trap region, which is verified based on a second reference voltage between the second and third threshold voltage groups;

controlling the second latch data, using data depending on the threshold voltage of the first charge trap region, which is verified based on the second reference voltage;

controlling the first latch data using the second latch data; and

verifying the first latch data.

22. The reading method according to claim 19 , wherein reading the third data bit comprises:

setting the first and second latch data;

controlling the second latch data using data depending on the threshold voltage of the second charge trap region, which is verified based on a first reference voltage between the first and second threshold voltage groups;

controlling the first latch data using the second latch data;

flopping the first latch data, using data depending on a threshold voltage of the second charge trap region, which is verified based on a second reference voltage between the second and third threshold voltage groups;

inversely flopping the first latch data, using data depending on the threshold voltage of the first charge trap region, which is verified based on the first reference voltage, where the first latch data is inversely flopped in response to the flopped second latch data; and

verifying the first latch data obtained from the controlled first latch data and from the inversely flopped first latch data.

23. The reading method according to claim 17 , wherein the non-volatile semiconductor memory device is a NOR-type memory device.

24. The reading method according to claim 17 , wherein the non-volatile semiconductor memory device is a NAND-type memory device.