Methods of forming dual-damascene interconnect structures on semiconductor substrates using multiple planarization layers having different porosity characteristics
View Patent ↗Methods of forming integrated circuit devices include patterning an electrically insulating layer to support dual-damascene interconnect structures therein. The steps of patterning the electrically insulating layer include using multiple planarization layers having different porosity characteristics. Forming an interconnect structure within an integrated circuit device may include forming an electrically insulating layer on a substrate and forming at least one via hole extending at least partially through the electrically insulating layer. The at least one via hole is filled with a first electrically insulating material having a first porosity. The filled at least one via hole is then covered with a second electrically insulating material layer having a second porosity lower than the first porosity. The second electrically insulating material layer is selectively etched back to expose a first portion of the first electrically insulating material in the at least one via hole. The electrically insulating layer is selectively etched to define a trench therein that exposes a second portion of the first electrically insulating material in the at least one via hole.
1. A method of forming an integrated circuit device, comprising the steps of:
forming an electrically insulating layer on a substrate;
forming at least one via hole extending at least partially through the electrically insulating layer;
filling the at least one via hole with a first electrically insulating material having a first porosity;
covering the filled at least one via hole with a second electrically insulating material layer having a second porosity lower than the first porosity;
selectively etching back the second electrically insulating material layer to expose a first portion of the first electrically insulating material in the at least one via hole;
selectively etching back the electrically insulating layer, using the etched second electrically insulating material layer as an etching mask, to define a trench therein that exposes a second portion of the first electrically insulating material in the at least one via hole; and then
removing the first electrically insulating material from the at least one via hole and the second electrically insulating material layer.
2. The method of claim 1 , wherein said covering step is preceded by a step of etching back the first electrically insulating material by chemical-mechanical polishing.
3. The method of claim 1 , wherein said covering step is preceded by a step of etching back the first electrically insulating material by reactive ion etching (RIE).
4. The method of claim 1 , wherein said step of selectively etching back the second electrically insulating material layer comprises selectively etching back the second electrically insulating material layer and the first electrically insulating material in sequence; and wherein said step of selectively etching back the electrically insulating layer comprises selectively etching back the electrically insulating layer and the first electrically insulating material simultaneously to define the trench.
5. The method of claim 4 , wherein said step of selectively etching back the electrically insulating layer comprises etching back the electrically insulating layer by reactive ion etching (RIE) the electrically insulating layer and the first electrically insulating material.
6. The method of claim 4 , wherein said step of forming the at least one via hole is preceded by a step of depositing a hard mask layer on the electrically insulating layer.
7. The method of claim 6 , wherein said covering step is preceded by a step of etching back the first electrically insulating material by chemical-mechanical polishing the first electrically insulating material for a sufficient duration to expose the hard mask layer.
8. The method of claim 7 , wherein said step of selectively etching back the second electrically insulating material layer comprises selectively etching back the second electrically insulating material layer for a sufficient duration to expose the hard mask layer.
9. A method of forming an integrated circuit device, comprising the steps of:
forming an intermetal dielectric (IMD) layer on a semiconductor substrate;
forming a via hole extending through the IMD layer;
forming a first electrically insulating material layer having a first porosity that extends on an upper surface of the IMD layer and fills the via hole;
planarizing the first electrically insulating material layer for a sufficient duration to expose the IMD layer and define an electrically insulating plug having the first porosity in the via hole;
depositing a second electrically insulating material layer having a second porosity lower than the first porosity that extends on the upper surface of the IMD layer and contacts the electrically insulating plug;
selectively etching the second electrically insulating material layer and the electrically insulating plug for a sufficient duration to expose the upper surface of the IMD layer and define a recessed electrically insulating plug in the via hole;
selectively etching back the IMD layer and the recessed electrically insulating plug, using the etched second electrically insulating material layer as an etching mask, to define a trench therein having a bottom that exposes a further recessed electrically insulating plug; and
removing the further recessed electrically insulating plug from the via hole and the second electrically insulating material layer.
10. The method of claim 9 , wherein removing the further recessed electrically insulating plug comprises removing the further recessed electrically insulating plug from the via hole using an ashing process.
11. The method of claim 9 , wherein a ratio of the first porosity to the second porosity is greater than about 2.0.