Stress liner for integrated circuits
View Patent ↗In one embodiment, a self-aligned contact (SAC) trench structure is formed through a dielectric layer to expose an active region of a MOS transistor. The SAC trench structure not only exposes the active region for electrical connection but also removes portions of a stress liner over the active region. This leaves the stress liner mostly on the sidewall and top of the gate of the MOS transistor. Removing portions of the stress liner over the active region substantially removes the lateral component of the strain imparted by the stress liner on the substrate, allowing for improved drive current without substantially degrading a complementary MOS transistor.
1. A method of forming an integrated circuit structure, the method comprising:
forming a gate of a first MOS transistor over a substrate;
forming active regions of the first MOS transistor in the substrate;
forming a stress liner over the gate and active regions of the first MOS transistor, the stress liner imparting strain on the substrate to increase a drive current of the first MOS transistor;
forming a dielectric layer over the gate and the active regions of the first MOS transistor; and
forming a trench structure over each of the active regions of the first MOS transistor through the dielectric layer such that each of the active regions of the first MOS transistor is exposed for an electrical connection and portions of the stress liner over each of the active regions of the first MOS transistor are removed.
2. The method of claim 1 further comprising:
forming a gate of a second MOS transistor over the substrate, the first and second MOS transistors being complementary MOS transistors;
forming active regions of the second MOS transistor in the substrate, wherein the stress liner formed over the gate and active regions of the first MOS transistor is also formed over the gate and active regions of the second MOS transistor; and
forming a trench structure over each of the active regions of the second MOS transistor through the dielectric layer such that each of the active regions of the second MOS transistor is exposed for an electrical connection and portions of the stress liner over each of the active regions of the second MOS transistor are removed.
3. The method of claim 1 wherein forming the active regions of the first MOS transistor comprises:
forming disposable spacers on sidewalls of the gate of the first MOS transistor;
implanting dopants in the substrate using the disposable spacers for alignment; and
removing the disposable spacers before the stress liner is formed over the gate and active regions of the first MOS transistor.
4. The method of claim 1 wherein the first MOS transistor comprises an NMOS transistor and wherein the stress liner imparts tensile strain on the substrate.
5. The method of claim 1 wherein the first MOS transistor comprises a PMOS transistor and wherein the stress liner imparts compressive strain on the substrate.
6. The method of claim 1 wherein the stress liner comprises silicon nitride.
7. The method of claim 1 wherein the stress liner comprises a material that is not appreciably etched by an etchant used to etch the dielectric layer to form a trench structure over each of the active regions of the first MOS transistor.
8. The method of claim 2 wherein the first MOS transistor comprises an NMOS transistor and the second MOS transistor comprises a PMOS transistor.
9. A method of forming an integrated circuit structure, the method comprising:
forming a gate of a first MOS transistor and a second MOS transistor, the first and second MOS transistors being a complementary pair of MOS transistors;
forming spacers on sidewalls of the gates of the first and second MOS transistors;
forming active regions of the first and second MOS transistors using the spacers for alignment;
removing the spacers from the sidewalls of the gates of the first and second MOS transistors;
forming a same stress liner over the gates and active regions of the first and second MOS transistors, the stress liner imparting strain on the substrate;
forming a dielectric layer over the gates and active regions of the first and second MOS transistors; and
forming a self-aligned contact (SAC) trench structure over each of the active regions of the first and second MOS transistors through the dielectric layer, the SAC trench structure removing substantial portions of the stress liner over an underlying active region and exposing the underlying active region.
10. The method of claim 9 wherein the stress liner imparts tensile strain on the substrate.
11. The method of claim 9 wherein the stress liner imparts compressive strain on the substrate.
12. The method of claim 9 wherein forming the SAC trench structure comprises:
etching the dielectric layer using an etchant that does not appreciably etch the stress liner.