Look-up table based logic macro-cells

1. A programmable look up table (LUT) structure for an integrated circuit, comprising a first stage and one or more intermediate stages and a last stage, wherein at least one of said intermediate stages or the last stage further comprises:

a primary input received in true and compliment logic levels, and an output; and

two LUT values, said primary input coupling one of said LUT values to said output, wherein at

least one of said LUT values further comprises:

a secondary input and a configurable data value; and

a programmable means to select either the secondary input or the data value as the LUT value.

2. The structure of claim 1 , wherein said secondary input is an output of a prior stage in the LUT structure.

3. The structure of claim 1 , wherein said configurable data value is an output of a configurable memory element.

4. The structure of claim 1 , wherein said configurable data value is further programmable to a logic zero or a logic one by said programmable means.

5. The structure of claim 3 , wherein said programmable means comprises a configuration circuit further comprised of one or more configurable memory elements.

6. The structure of claim 5 , wherein said configurable memory element is one of user configurable RAM element or a mask configurable ROM element.

7. The structure of claim 5 , wherein said memory element is one of fuse link, anti-fuse capacitor, laser-fuse, SRAM cell, DRAM cell, metal optional link, EPROM cell, EEPROM cell, flash cell, ferro-electric element, optical element, electro-chemical element, electrolytic element, Carbon nano-tube, electro-mechanical element, electro-magnetic element and magnetic element.

8. A programmable macro look up table (LUT) circuit for an integrated circuit, comprising:

one or more first LUT circuits comprised of:

a LUT output; and

M primary inputs, where M is an integer value greater than or equal to two, each said M inputs received in true and compliment logic levels; and

2 M LUT values, each said LUT values comprising a configurable data value at logic zero or logic one, wherein any given combination of said M primary input signal levels couples one of said LUT values to said LUT output; and

a second LUT circuits comprised of:

a LUT output; and

at least one primary input, said input received in true and compliment logic levels; and

at least two LUT values, wherein at least one LUT value is further comprised of:

an output of one of said first LUT circuits; and

a configurable data value at logic zero or logic one; and

a programmable means to select said first LUT circuit output or configurable data value as the LUT value;

wherein, said at least one primary input signal couples one of the LUT values to said LUT output.

9. The circuit of claim 8 , wherein said configurable data value is generated by an output of a configurable memory element.

10. The circuit of claim 8 , wherein said configurable data value is further programmable to said logic zero or logic one by said programmable means.

11. The circuit of claim 8 , wherein an (M+1) input generic LUT circuit is implemented by:

two first LUT circuits, each comprised of M inputs; and

one second LUT circuit with one primary input;

wherein, the outputs of the two first LUT circuits are programmed as the two LUT values for the second LUT circuit.

12. The circuit of claim 8 , wherein an (M+1) input special LUT circuit is implemented by:

one first LUT circuit comprised of M inputs; and

one configurable data value; and

one second LUT circuit with one primary input;

wherein, the output of the first LUT circuit and the configurable data value are programmed as the two LUT values for the second LUT circuit.

13. The circuit of claim 10 , wherein said programmable means further comprises a configuration circuit comprised of one or more configurable memory elements.

14. The circuit of claim 13 , wherein said configurable memory element is one of user configurable random access memory (RAM) element or a mask configurable read only memory (ROM) element.

15. The circuit of claim 13 , wherein said memory element is one of fuse link, anti-fuse capacitor, laser-fuse, SRAM cell, DRAM cell, metal optional link, EPROM cell, EEPROM cell, flash cell, ferro-electric element, optical element, electro-chemical element, electrolytic element, Carbon nano-tube, electro-mechanical element, electro-magnetic element and magnetic element.

16. The circuit of claim 13 , further comprising a silicon substrate layer, wherein the first and second LUT circuits further comprises a transistor constructed on said substrate layer, and wherein said configuration memory element is constructed above the silicon substrate layer.

17. The circuit of claim 13 , further comprising a first metal layer, wherein the first and second LUT circuits further comprises a transistor constructed on a thin film layer, and wherein said transistor and the configuration memory element are constructed above the first metal layer.

18. A programmable look up table (LUT) structure for an integrated circuit, comprising a first stage and one or more intermediate stages and a last stage, wherein the last stage further comprises:

a primary input, said input received in true and compliment logic levels; and

a first and a second output; and

a first and a second LUT value, each said LUT values further comprised of:

a secondary input, said input generated by an output from a prior LUT stage; and

a configurable data value at logic zero or logic one; and

a programmable means to couple the secondary input or the data value to said LUT value;

wherein, said primary input couples one of the LUT values to said first output; and

wherein said programmable means further provides the means to couple one or both of:

the secondary input of the first LUT value to said second output;

the secondary input of the second LUT value to said second output.

19. The structure of claim 18 , further comprising a third output, wherein said programmable means further provides the means to couple one or both of:

the secondary input of the first LUT value to said third output;

the secondary input of the second LUT value to said third output.

20. The structure of claim 18 , further comprising a configuration circuit, wherein the configuration circuit comprises a random access memory (RAM) element or a read only memory (ROM) element.