IP Library Granted Patent US 7,407,888
Granted Patent B2
US 7,407,888 · App. 11/355,992 · Granted Aug 5, 2008

Semiconductor device and a fabrication process thereof

Assignee: Fujitsu Limited
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Quick Facts
Patent No.
US 7,407,888
App. No.
11/355,992
Granted
Aug 5, 2008
Kind
B2
Abstract

A method of fabricating a semiconductor device comprises the steps of forming a contact hole in an insulation film so as to extend therethrough and so as to expose a conductor body at a bottom part of the contact hole, forming a barrier metal film of tungsten nitride on the bottom part and a sidewall surface of the contact hole with a conformal shape to the bottom part and the sidewall surface of the contact hole, forming a tungsten layer so as to fill the contact hole via the barrier metal film, and forming a tungsten plug in the contact hole by the tungsten layer by polishing away a part of the tungsten film on the insulation film until a surface of the insulation film is exposed, wherein there is conducted a step of cleaning a surface of the conductor body prior to the forming step of the barrier metal film.

Claims (18)

1. A method of fabricating a semiconductor device having a contact structure comprising a conductor body, an insulation film covering said conductor body, and a contact plug penetrating through said insulation film and electrically connected to said conductor body, said method comprising the steps of:

forming a contact hole in said insulation film to extend therethrough and to expose said conductor body at a bottom part of said contact hole;

forming a barrier metal film of tungsten nitride over said bottom part and a sidewall surface of said contact hole with a conformal shape to said bottom part and said sidewall surface of said contact hole;

forming a tungsten layer to fill said contact hole via said barrier metal film; and

forming a tungsten plug in said contact hole by said tungsten layer by polishing away a part of said tungsten film over said insulation film until a surface of said insulation film is exposed,

wherein there is conducted a step of cleaning a surface of said conductor body prior to said forming step of said barrier metal film,

said barrier metal film is formed such that a nitrogen concentration therein decreases from a first side thereof contacting with said bottom surface and said sidewall surface of said contact hole to a second side contacting with said tungsten plug, and

said barrier metal film causes transition to said tungsten plug continuously at said second side.

2. The method as claimed in claim 1 , wherein said conductor body comprises a refractory metal silicide of any of NiSi, CoSi 2 , TaSi 2 , TiSi 2 and PtSi.

3. The method as claimed in claim 1 , wherein said step of forming said barrier metal film is conducted such that a flow rate of a process gas used for a nitrogen source is set to a first flow rate when commencing formation of said barrier metal film, followed by gradual decrease of flow rate of said processing gas, such that said processing gas is supplied with a second flow rate smaller than said first flow rate at an end of forming said barrier metal film.

4. The methods as claimed in claim 1 , wherein said step of forming said barrier metal film is conducted by using a WF 6 gas, a NH 3 gas, an Ar gas, and any of a SiH 4 gas and a B 2 H 6 gas for a processing gas.

5. The method as claimed in claim 1 , wherein said step of forming said tungsten layer is conducted by using a WF 6 gas, an Ar gas and any of a SiH 4 gas and a B 2 H 6 gas as a processing gas.

6. The method as claimed in claim 1 , wherein said cleaning step is conducted by a sputter-etching process in an ambient of a rare gas and a hydrogen gas.

7. The method as claimed in claim 1 , wherein said cleaning step is conducted by a sputtering process in a rare gas ambient.

8. The method as claimed in claim 1 , wherein said cleaning step is conducted by an etching process in NF 3 or hydrogen plasma.

9. The method as claimed in claim 1 , wherein said semiconductor device is a logic semiconductor device having a diffusion region and a gate electrode, any of said diffusion region and said gate electrode is covered by a refractive silicide film, said contact structure being formed on said diffusion region and said gate electrode, said refractory silicide film being used as said conductor body.

10. The method as claimed in claim 1 , wherein said semiconductor device includes a multilayer interconnection structure, said multilayer interconnection structure comprising a first interconnection layer and a second interconnection layer formed over said first interconnection layer via an interlayer insulation film, said contact structure being formed in said multilayer interconnection structure while using said first interconnection layer as said conductor body, such that said contact plug connects said first interconnection layer to said second interconnection layer.

11. The method as claimed in claim 1 , wherein said step of cleaning causes etching in said surface of said conductor body with a depth of 5 -8 nm.

Assignments (4)
CHANGE OF ADDRESS Recorded Dec 23, 2016
From: FUJITSU SEMICONDUCTOR LIMITED
To: FUJITSU SEMICONDUCTOR LIMITED
Reel/Frame 041188/0401 →
CHANGE OF NAME Recorded Jul 9, 2010
From: FUJITSU MICROELECTRONICS LIMITED
To: FUJITSU SEMICONDUCTOR LIMITED
Reel/Frame 024651/0744 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 9, 2008
From: FUJITSU LIMITED
To: FUJITSU MICROELECTRONICS LIMITED
Reel/Frame 021976/0089 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 17, 2006
From: ITO, TAKESHI; INAGAKI, SATOSHI; UCHINO, YASUNORI; KAWAMURA, KAZUO
To: FUJITSU LIMITED
Reel/Frame 017591/0282 →
Priority Claims (2)
JP 2005-177220 · Jun 17, 2005 · national
JP 2006-006292 · Jan 13, 2006 · national
Continuity (1)
Related Publication 20060284317A1 · Dec 21, 2006