Semiconductor device assemblies including face-to-face semiconductor dice and systems including such assemblies
Semiconductor device assemblies include at least first and second semiconductor dice disposed in a face-to-face configuration. At least some of a plurality of conductive structures are electrically and structurally coupled to a bond pad of the first semiconductor die and a bond pad of the second semiconductor die. A first end of each of a plurality of laterally extending conductive elements may be structurally and electrically coupled to a conductive terminal of a substrate, and a second end of each laterally extending conductive element is structurally and electrically coupled to at least one of a bond pad of the first semiconductor die, a bond pad of the second semiconductor die, and a conductive structure. Methods include the fabrication of such assemblies. Electronic systems include at least one electronic signal processing device, at least one input or output device, and at least one memory device including such a semiconductor device assembly.
1. A semiconductor device assembly comprising:
a substrate including a plurality of conductive terminals disposed on or in a surface thereof;
a first semiconductor die including an active surface and a plurality of bond pads disposed in a first selected connection pattern on or in the active surface;
a second semiconductor die including an active surface and a plurality of bond pads disposed in a second selected connection pattern on or in the active surface of the second semiconductor die, the active surface of the first semiconductor die facing the active surface of the second semiconductor die;
a plurality of conductive structures, each conductive structure of the plurality being electrically and structurally coupled to a bond pad of the first semiconductor die and a bond pad of the second semiconductor die;
a plurality of laterally extending conductive elements, a first end of each laterally extending conductive element being structurally and electrically coupled to a conductive terminal of the substrate, a second end of each laterally extending conductive element being structurally and electrically coupled to at least one of a bond pad of the first semiconductor die, a bond pad of the second semiconductor die, and a conductive structure of the plurality of conductive structures; and
a plurality of discrete dielectric structures disposed between and in contact with each of the active surface of the first semiconductor die and the active surface of the second semiconductor die; wherein an intermediate portion of at least one laterally extending conductive element of the plurality of laterally extending conductive elements, between the first end and the second end of the at least one laterally extending conductive element of the plurality, passes through at least one discrete dielectric structure of the plurality of discrete dielectric structures; wherein each discrete dielectric structure is in physical contact with both the active surface of the first semiconductor die and the active surface of the second semiconductor die.
2. The semiconductor device assembly of claim 1 , wherein the second selected connection pattern is a mirror image of the first selected connection pattern.
3. The semiconductor device assembly of claim 1 , wherein the second selected connection pattern is identical to the first selected connection pattern.
4. The semiconductor device assembly of claim 1 , wherein each laterally extending conductive element of the plurality comprises a bond wire.
5. The semiconductor device assembly of claim 1 , wherein the second end of each laterally extending conductive element is disposed between and structurally and electrically coupled to both a bond pad of the first semiconductor die and a conductive structure.
6. The semiconductor device assembly of claim 1 , wherein a portion of each laterally extending conductive element passes through at least one dielectric structure, each dielectric structure configured to position the portion of the laterally extending conductive element between the active surface of the first semiconductor die and the active surface of the second semiconductor die to prevent contact between the laterally extending conductive element and the active surface of the first semiconductor die and the active surface of the second semiconductor die.
7. The semiconductor device assembly of claim 1 , wherein each dielectric structure of the plurality is disposed proximate a lateral edge of at least one of the first semiconductor die and the second semiconductor die.
8. The semiconductor device assembly of claim 1 , wherein a portion of only one laterally extending conductive element extends through each discrete dielectric structure.
9. The semiconductor device assembly of claim 1 , wherein the plurality of bond pads of the first semiconductor die is disposed substantially along a centerline of the first semiconductor die and the plurality of bond pads of the second semiconductor die is disposed substantially along a centerline of the second semiconductor die.
10. The semiconductor device assembly of claim 1 , wherein the plurality of bond pads of the first semiconductor die is disposed proximate a lateral edge of the first semiconductor die and the plurality of bond pads of the second semiconductor die is disposed proximate a lateral edge of the second semiconductor die.
11. The semiconductor device assembly of claim 10 , wherein each conductive structure comprises a solder bump.
12. The semiconductor device assembly of claim 1 , wherein a back side of the first semiconductor die is attached to the substrate.
13. The semiconductor device assembly of claim 1 , wherein the substrate comprises one of a circuit board, an interposer, a semiconductor die, and a semiconductor wafer.
14. The semiconductor device assembly of claim 1 , further comprising at least one additional semiconductor die.
15. The semiconductor device assembly of claim 14 , wherein the at least one additional semiconductor die comprises:
a third semiconductor die including an active surface and a plurality of bond pads disposed in a third selected connection pattern on or in the active surface;
a fourth semiconductor die including an active surface and a plurality of bond pads disposed in a fourth selected connection pattern on or in the active surface, the active surface of the first additional semiconductor die facing the active surface of the second additional semiconductor die.
16. The semiconductor device assembly of claim 15 , further comprising:
an additional plurality of conductive structures, each conductive structure of the additional plurality being electrically and structurally coupled to a bond pad of the third semiconductor die and the fourth semiconductor die; and
an additional plurality of laterally extending conductive elements, each laterally extending conductive element of the additional plurality including a first end structurally and electrically coupled to a conductive terminal of the substrate and a second end structurally and electrically coupled to at least one of a bond pad of the third semiconductor die, a bond pad of the fourth semiconductor die, and a conductive structure of the additional plurality.
17. The semiconductor device assembly of claim 15 , wherein a back side of the third semiconductor die is attached to a back side of the second semiconductor die.
18. The semiconductor device assembly of claim 1 , further comprising a dielectric encapsulant material substantially enclosing the first semiconductor die and the second semiconductor die.
19. An electronic system comprising:
at least one electronic signal processing device;
at least one memory device configured to communicate electrically with the at least one electronic signal processing device; the at least one memory device comprising a semiconductor device assembly, the semiconductor device assembly comprising:
a substrate including a plurality of conductive terminals disposed on or in a surface thereof;
a first semiconductor die including an active surface and a plurality of bond pads disposed in a first selected connection pattern on or in the active surface;
a second semiconductor die including an active surface and a plurality of bond pads disposed in a second selected connection pattern on or in the active surface, the active surface of the first semiconductor die facing the active surface of the second semiconductor die;
a plurality of conductive structures, each conductive structure of the plurality being electrically and structurally coupled to a bond pad of the first semiconductor die and to a bond pad of the second semiconductor die;
a plurality of laterally extending conductive elements, a first end of each laterally extending conductive element being structurally and electrically coupled to a conductive terminal of the substrate, a second end of each laterally extending conductive element being structurally and electrically coupled to at least one of a bond pad of the first semiconductor die, a bond pad of the second semiconductor die, and a conductive structure; and
a plurality of discrete dielectric structures disposed between and in contact with each of the active surface of the first semiconductor die and the active surface of the second semiconductor die; wherein an intermediate portion of at least one laterally extending conductive element of the plurality of laterally extending conductive elements, between the first end and the second end of the at least one laterally extending conductive element of the plurality, passes through at least one discrete dielectric structure of the plurality of discrete dielectric structures; wherein each discrete dielectric structure is in physical contact with both the active surface of the first semiconductor die and the active surface of the second semiconductor die; and
at least one of an input device and an output device configured to communicate electrically with at least one of the memory device and the electronic signal processing device.
20. The electronic system of claim 19 , wherein the second selected connection pattern is a mirror image of the first selected connection pattern.
21. The electronic system of claim 19 , wherein each laterally extending conductive element of the plurality comprises a bond wire.
22. The electronic system of claim 19 , wherein the second end of each laterally extending conductive element is disposed between and structurally and electrically coupled to both a bond pad of the first semiconductor die and a conductive structure.
23. The electronic system of claim 19 , wherein a portion of only one laterally extending conductive element extends through each discrete dielectric structure.
24. The electronic system of claim 19 , wherein a portion of each laterally extending conductive element passes through at least one dielectric structure, each dielectric structure configured to position the portion of the laterally extending conductive element between the active surface of the first semiconductor die and the active surface of the second semiconductor die to prevent contact between the laterally extending conductive element and the active surface of the first semiconductor die and the active surface of the second semiconductor die.
25. The electronic system of claim 19 , wherein each dielectric structure of the plurality is disposed proximate a lateral edge of at least one of the first semiconductor die and the second semiconductor die.
26. The electronic system of claim 19 , wherein the plurality of bond pads of the first semiconductor die is disposed substantially along a centerline of the first semiconductor die and the plurality of bond pads of the second semiconductor die is disposed substantially along a centerline of the second semiconductor die.
27. The electronic system of claim 19 , wherein the plurality of bond pads of the first semiconductor die is disposed is an array on the active surface of the first semiconductor die and the plurality of bond pads of the second semiconductor die is disposed in an array on the active surface of the second semiconductor die.
28. The electronic system of claim 27 , wherein each conductive structure comprises a solder bump.
29. The electronic system of claim 19 , wherein a back side of the first semiconductor die is attached to the substrate.
30. The electronic system of claim 19 , wherein the substrate comprises a circuit board.
31. The electronic system of claim 19 , further comprising at least one additional semiconductor die.
32. The electronic system of claim 31 , wherein the at least one additional semiconductor die comprises:
a third semiconductor die including an active surface and a plurality of bond pads disposed in a third selected connection pattern on or in the active surface;
a fourth semiconductor die including an active surface and a plurality of bond pads disposed in a fourth selected connection pattern on or in the active surface, the active surface of the third semiconductor die facing the active surface of the fourth semiconductor die.
33. The electronic system of claim 32 , further comprising:
an additional plurality of conductive structures, each conductive structure of the additional plurality being electrically and structurally coupled to a bond pad of the third semiconductor die and the fourth semiconductor die; and
an additional plurality of laterally extending conductive elements, each laterally extending conductive element of the additional plurality including a first end structurally and electrically coupled to a conductive terminal of the substrate and a second end structurally and electrically coupled to at least one of a bond pad of the third semiconductor die, a bond pad of the fourth semiconductor die, and a conductive structure of the additional plurality.
34. The electronic system of claim 32 , wherein a back side of the third semiconductor die is attached to a back side of the second semiconductor die.
35. The electronic system of claim 19 , further comprising a dielectric encapsulant material substantially enclosing the first semiconductor die and the second semiconductor die.