Semiconductor device and method of manufacturing the same
The present invention relates to a semiconductor device that includes a semiconductor substrate ( 10 ) having source/drain diffusion regions ( 14 ) formed therein and control gates ( 20 ) formed thereon, with grooves ( 18 ) being formed on the surface of the semiconductor substrate ( 10 ) and being located below the control gates ( 20 ) and between the source/drain diffusion regions ( 14 ). The grooves ( 18 ) are separated from the source/drain diffusion regions ( 14 ), thereby increasing the effective channel length to maintain a constant channel length for charge accumulation while enabling the manufacture of smaller memory cells. The present invention also provides a method of manufacturing the semiconductor device.
1. A semiconductor device comprising:
a semiconductor substrate including source/drain diffusion regions formed therein to extend in a first direction, the semiconductor substrate further including channel regions defined between the source/drain regions and extending in the first direction;
an ONO film formed on the semiconductor substrate over the channel regions and the source/drain regions; and
a control gate provided on the ONO film and extending in a second direction perpendicular to the first direction, the control gate provided over portions of the channel regions and the source/drain regions,
wherein the semiconductor substrate has a groove formed below the control gate and located in the channel regions between the source/drain diffusion regions, the groove being separated from the source/drain diffusion regions by a predetermined distance.
2. The semiconductor device as claimed in claim 1 , wherein each of the source/drain diffusion regions is self aligned with the groove adjacent thereto.
3. The semiconductor device as claimed in claim 1 , wherein the source/drain diffusion regions also serve as bit lines.
4. The semiconductor device as claimed in claim 1 , wherein the ONO film is in contact with a surface of the groove.