Ceramic circuit substrate and manufacturing method thereof
View Patent ↗A ceramic circuit substrate and a manufacturing method thereof are provided, which has excellent thermal shock tolerance by forming a gap between a circuit pattern section and a ceramic substrate, and has a capability of preventing etchant residue from remaining therein. The ceramic circuit substrate according to the present invention includes patterns of brazing material ( 8 and 9 ) formed on the ceramic substrate, and a circuit pattern section jointed to the patterns of brazing material. The patterns of brazing material includes a line pattern along the edge of the circuit pattern. Also, a gap is formed within the line pattern located between the ceramic substrate and the circuit pattern.
1. A ceramic circuit substrate comprising:
a ceramic substrate;
a pattern of brazing material formed on the ceramic substrate; and
a metal plate jointed onto the pattern of brazing material,
wherein a gap is formed between the ceramic substrate and the metal plate,
wherein the pattern of brazing material includes a bordering pattern formed along an edge of the metal plate, and the bordering pattern has a width of 0.05 to 2 mm and a thickness of about 5 to 30 μm,
wherein the gap is surrounded by the ceramic substrate, the metal plate, and the bordering pattern, and
wherein nickel plating or nickel alloy plating is performed on the metal plate.
2. The ceramic circuit substrate according to claim 1 , wherein the metal plate is a circuit pattern.
3. The ceramic circuit substrate according to claim 1 , wherein the pattern of brazing material further includes a spot pattern allocated in the gap and disposed within the bordering pattern.
4. The ceramic circuit substrate according to claim 1 , wherein the width of the bordering pattern is 0.1 to 1.5 mm.
5. The ceramic circuit substrate according to claim 1 , wherein the bordering pattern has non-uniform width.
6. The ceramic circuit substrate according to claim 1 , wherein the bordering pattern encloses the gap.
7. The ceramic circuit substrate according to claim 1 , wherein the pattern of brazing material is provided such that fluid communication between the gap and an atmosphere exterior to the gap is prevented.
8. The ceramic circuit substrate according to claim 1 , wherein the thickness of the bordering pattern is approximately 20 μm.
9. The ceramic circuit substrate according to claim 1 , wherein the thickness of the bordering pattern is 20 μm.
10. A ceramic circuit substrate comprising:
a ceramic substrate;
a pattern of brazing material formed on the ceramic substrate;
a metal plate jointed onto the pattern of brazing material; and
a gap formed in between the ceramic substrate and the metal plate,
wherein the pattern of brazing material includes a bordering pattern formed along the edge of the metal plate, and the gap is located within the bordering pattern,
wherein bordering pattern has a width of 0.05 to 2 mm and a thickness of about 5 to 30 μm, and
wherein nickel plating or nickel alloy plating is performed on the metal plate.
11. The ceramic circuit substrate according to claim 10 , wherein the metal plate is a circuit pattern.
12. The ceramic circuit substrate according to claim 10 , wherein the pattern of brazing material further includes a spot pattern allocated in the gap and disposed within the bordering pattern.
13. The ceramic circuit substrate according to claim 10 , wherein the width of the bordering pattern is 0.1 to 1.5 mm.
14. The ceramic circuit substrate according to claim 10 , wherein the bordering pattern has non-uniform width.
15. The ceramic circuit substrate according to claim 10 , wherein the bordering pattern encloses the gap.
16. The ceramic circuit substrate according to claim 10 , wherein the pattern of brazing material is provided such that fluid communication between the gap and an atmosphere exterior to the gap is prevented.
17. The ceramic circuit substrate according to claim 10 , wherein the thickness of the bordering pattern is approximately 20 μm.
18. The ceramic circuit substrate according to claim 10 , wherein the thickness of the bordering pattern is 20 μm.