Methods and circuits for driving large off-chip loads
View Patent ↗A method and system to drive large off-chip loads, such as, for example, laser diodes, wherein the system includes an integrated circuit coupled to an external differential diode load. Alternatively, the external diode load may be driven single-ended. The integrated circuit includes a data buffer device and a clock buffer device. The integrated circuit also includes a multiplexer device coupled to the clock buffer device configured to multiplex a data input signal and a clock input signal received at respective inputs of the integrated circuit. If the external diode is single-ended, the data input signal is transmitted to the data buffer device, which is then used solely to drive the diode load. If the diode load is differential, the data buffer device receives the data input signal. At the same time, the multiplexer device receives both the data input signal and the clock input signal and selects the data signal to drive the clock buffer device. For a diode load being driven differentially, the outputs of the two buffer devices are merged together externally through the use of a power-combining network, which includes external or off-chip transmission lines, which carry a respective output signal for the data buffer device and the clock buffer device.
1. A system for driving a device load, the system comprising:
an integrated circuit comprising:
a first input configured for receiving a data signal;
a second input configured for receiving a clock signal;
a multiplexer configured for:
receiving the data signal and the clock signal; and
for a device load driven differentially, outputting the data signal as a multiplexed signal to a clock buffer device;
the clock buffer device configured for receiving the multiplexed signal and outputting the multiplexed signal to a power network; and
a data buffer device configured for:
receiving the data signal, wherein the received data signal is transmitted from the first input of the integrated circuit to the data buffer device without passing through the multiplexer; and
outputting the received data signal to the power network; and
the power network to couple said integrated circuit to said device load, the power network configured for receiving the data signal from the data buffer device and receiving the multiplexed signal from the clock buffer device for driving the device load, the device load being coupled to the power network at both ends of the device load.
2. The system according to claim 1 , wherein said device load is a laser diode.
3. The system according to claim 1 , wherein the power network comprises a first transmission line pair, coupled to said data buffer device at a first end, and a second transmission line pair, coupled to said clock buffer device at a first end, a second end of said first and second transmission line pairs being coupled to a third transmission line pair at a first end, and said third transmission line pair being coupled to said device load at a second end.
4. The system according to claim 3 , wherein each line of said first transmission line pair comprises a characteristic impedance of Z 1 , each line of said second transmission line pair comprises a characteristic impedance of Z 2 , and each line of said third transmission line pair comprises a characteristic impedance of Z 3 , wherein Z 1 =Z 2 and ½(Z 1 )=Z 3 .
5. The system according to claim 1 , wherein the integrated circuit further comprises a stage prior to the data buffer device to equalize delays and signal swings of respective outputs of said data buffer device and said clock buffer device.
6. The system according to claim 1 , wherein the integrated circuit comprises a 10-gigabit Ethernet integrated circuit.
7. The system of claim 1 , wherein the device load comprises a plurality of respective impedance termination values.
8. The system of claim 1 , wherein the outputs of the data buffer device and the clock buffer device are merged together through the power network which carries a respective output signal for the data buffer device and the clock buffer device.
9. The system of claim 1 , wherein the multiplexer is further configured for:
for a device load not driven differentially, outputting the clock signal as the multiplexed signal to the clock buffer device.
10. A method for driving a device load, the method comprising:
providing an integrated circuit comprising:
a first input configured for receiving a data signal;
a second input configured for receiving a clock signal;
a multiplexer configured for:
receiving the data signal and the clock signal; and
for a device load driven differentially, outputting the data signal as a multiplexed signal to a clock buffer device;
the clock buffer device configured for receiving the multiplexed signal and outputting the multiplexed signal to a power network; and
a data buffer device configured for:
receiving the data signal, wherein the received data signal is transmitted from the first input of the integrated circuit to the data buffer device without passing through the multiplexer; and
outputting the received data signal to the power network; and
providing the power network to couple said integrated circuit to said device load, the power network configured for receiving the data signal from the data buffer device and receiving the multiplexed signal from the clock buffer device for driving the device load, the device load being coupled to the power network at both ends of the device load.
11. The method according to claim 10 , wherein said device load is a laser diode.
12. The method according to claim 10 , wherein the power network comprises a first transmission line pair, coupled to said data buffer device at a first end, and a second transmission line pair, coupled to said clock buffer device at a first end, a second end of said first and second transmission line pairs being coupled to a third transmission line pair at a first end, and said third transmission line pair being coupled to said device load at a second end.
13. The method according to claim 12 , wherein each line of said first transmission line pair comprises a characteristic impedance of Z 1 , each line of said second transmission line pair comprises a characteristic impedance of Z 2 , and each line of said third transmission line pair comprises a characteristic impedance of Z 3 , wherein Z 1 =Z 2 and ½(Z 1 )=Z 3 .
14. The method according to claim 10 , wherein the integrated circuit further comprises a stage prior to the data buffer device to equalize delays and signal swings of respective outputs of said data buffer device and said clock buffer device.
15. The method of claim 10 , wherein the device load comprises a plurality of respective impedance termination values.
16. The method of claim 10 , wherein the outputs of the data buffer device and the clock buffer device are merged together through the power network which carries a respective output signal for the data buffer device and the clock buffer device.
17. The method of claim 10 , wherein the multiplexer is further configured for:
for a device load not driven differentially, outputting the clock signal as the multiplexed signal to the clock buffer device.