Precision differential level shifter
View Patent ↗A differential level shifter employs a variable current mirror to maintain a reference voltage at one output while the other output follows a differential input. Resistor networks allow postproduction trimming of load resistors and the current mirror, resulting in a precise and accurate output of the differential signal. An active cascode circuit enhances current mirror balance and high frequency operation.
1. A circuit for shifting the reference level of a differential signal while preserving its amplitude, the circuit comprising: a negative input terminal;
a positive input terminal;
a first load resistor having a first end and a second end, the first end connected to the negative input terminal;
a second load resistor having a first end and a second end, the first end connected to the positive input terminal;
a first pass transistor having a first node, a second node and a control node, the first node connected to the second end of the first load resistor to form a negative output terminal, the control node connected to a selected reference voltage signal;
a current mirror having a first current node, a second current node and a current control node, the first current node connected to the second node of the first pass transistor, the second current node connected to the second end of the second load resistor to form a positive output terminal; and
a first amplifier having a negative input, a positive input and an output, the positive input connected to the negative output terminal, the negative input connected to the selected reference voltage signal, the output connected to the current control node of the current mirror.
2. The circuit of claim 1 , further comprising an active cascode circuit connected to the first and second current nodes of the current mirror and to the second end of the second load resistor at the positive output terminal.
3. The circuit of claim 2 , wherein the active cascode circuit comprises:
a second pass transistor having a control node, the second pass transistor connected in series between the second end of the second load resistor and the second current node of the current mirror; and
a second amplifier having a negative input, a positive input and an output, the negative input of the second amplifier connected to the second current node of the current mirror, the positive input of the second amplifier connected to the first current node of the current mirror, and output of the second amplifier connected to the control node of the second pass transistor.
4. The circuit of claim 3 , wherein the first and second amplifiers comprise a voltage operational amplifier, a Norton operation amplifier, an operational transconductance amplifier and/or a differential amplifier.
5. The circuit of claim 1 , wherein the current mirror comprises one or more bipolar transistors and/or metal oxide semiconductor transistors.
6. The circuit of claim 1 , wherein at least one of the two load resistors comprises a trimmable resistor capable of adjusting the load resistors to have substantially equal resistance values.
7. The circuit of claim 1 , wherein at least one of the load resistors comprises a series string of resistors, at least one of the resistors in the series string being connected in parallel with a switchable resistor network comprising a parallel connection of resistors, each connected in series with a switch, wherein the resistance values of the series string of resistors vary according to a geometric progression with a common ratio substantially equal to about ½.
8. The circuit of claim 1 , further comprising a reference voltage source that provides the selected reference voltage signal.
9. A circuit for shifting the reference level of a differential signal while preserving its amplitude, the circuit comprising:
a negative input terminal;
a positive input terminal;
a first load resistor having a first end and a second end, the first end connected to the negative input terminal;
a second load resistor having a first end and a second end, the first end connected to the positive input terminal,
wherein at least one of the load resistors comprises a trimmable resistor;
a trimmable current mirror having a first current node, a second current node and a current control node, the current mirror configured to mirror the current passing through the first current node and the first load resistor and the current passing through the second current node and the second resistor such that the current passing through the first and second current nodes are mirrored to each other, the first current node connected to the second end of the first load resistor to form a negative output terminal, the second current node connected to the second end of the second load resistor to form a positive output terminal,
wherein the trimmable resistor comprises a series string of resistors, at least one of the resistors in the series string being connected in parallel with a switchable resistor network comprising a parallel connection of resistors, each connected in series with a switch, wherein the resistance values of the series string of resistors vary according to a geometric progression with a common ratio substantially equal to about ½.
10. The circuit of claim 9 , wherein the trimmable current mirror further comprises:
a plurality of current sources;
a plurality of switches; and
an offset resistor,
wherein the current sources, switches and offset resistor are connected in an H-bridge.
11. The circuit of claim 9 , wherein one of the load resistors comprises a non-trimmable resistor that is sized to correspond to about ½ the maximum resistance value that can be reached by the trimmable resistor.
12. A circuit for shifting the reference level of a differential signal while preserving its amplitude, the circuit comprising:
a negative input terminal;
a positive input terminal;
a first load resistor having a first end and a second end, the first end connected to the negative input terminal;
a second load resistor having a first end and a second end, the first end connected to the positive input terminal,
wherein at least one of the load resistors comprises a trimmable resistor;
a trimmable current mirror having a first current node, a second current node and a current control node, the trimmable current mirror configured to mirror the current passing through the first current node and the first load resistor and the current passing through the second current node and the second resistor such that the current passing through the first and second current nodes are mirrored to each other, the first current node connected to the second end of the first load resistor to form a negative output terminal, the second current node connected to the second end of the second load resistor to form a positive output terminal; and
a first pass transistor having a first node, a second node and a control node, the first node and second node connected in series between the second end of the first load resistor and the first current node of the trimmable current mirror.
13. The circuit of claim 12 , further comprising a first amplifier having a negative input, a positive input and an output, the negative input connected to a selected reference voltage signal, the positive input connected to the negative output terminal, and the output connected to the current control node of the current mirror.
14. The circuit of claim 13 , wherein the first amplifier comprises a voltage operational amplifier, a Norton operation amplifier, an operational transconductance amplifier or a differential amplifier.
15. A circuit for shifting the reference level of a differential signal while preserving its amplitude, the circuit comprising:
a negative input terminal;
a positive input terminal;
a first load resistor having a first end and a second end, the first end connected to the negative input terminal;
a second load resistor having a first end and a second end, the first end connected to the positive input terminal,
wherein at least one of the load resistors comprises a trimmable resistor;
a trimmable current mirror having a first current node, a second current node and a current control node, the current mirror configured to mirror the current passing through the first current node and the first load resistor and the current passing through the second current node and the second resistor such that the current passing through the first and second current nodes are mirrored to each other, the first current node connected to the second end of the first load resistor to form a negative output terminal, the second current node connected to the second end of the second load resistor to form a positive output terminal;
a pass transistor having a first node, a second node and a control node, the first node and second node connected in series between the second end of the second load resistor and the second current node of the trimmable current mirror; and
an amplifier having a negative input, a positive input and an output, the positive input of the amplifier connected to the first current node of the trimmable current mirror, the negative input of the amplifier connected to the second current node of the trimmable current mirror, and output of the second amplifier connected to the control node of the pass transistor.
16. The circuit of claim 15 , wherein the second amplifier comprises a voltage operational amplifier, a Norton operation amplifier, an operational transconductance amplifier or a differential amplifier.
17. The circuit of claim 9 , wherein the first load resistor is structured such that all or substantially all of the current that passes through the first load resistor also passes through the first current node of the trimmable current mirror, and all or substantially all of the current that passes through the first current node of the trimmable current mirror had previously passed through the first load resistor.
18. The circuit of claim 17 , wherein the second load resistor is structured such that all or substantially all of the current that passes through the second load resistor also passes through the second current node of the trimmable current mirror, and all or substantially all of the current that passes through the second current node of the trimmable current mirror had previously passed through the second load resistor.
19. The circuit of claim 12 , wherein the trimmable resistor comprises a series string of resistors, at least one of the resistors in the series string being connected in parallel with a switchable resistor network comprising a parallel connection of resistors, each connected in series with a switch, wherein the resistance values of the series string of resistors vary according to a geometric progression with a common ratio substantially equal to about ½.
20. The circuit of claim 12 , wherein the trimmable current mirror further comprises:
a plurality of current sources;
a plurality of switches; and
an offset resistor,
wherein the current sources, switches and offset resistor are connected in an H-bridge.
21. The circuit of claim 15 , wherein the trimmable resistor comprises a series string of resistors, at least one of the resistors in the series string being connected in parallel with a switchable resistor network comprising a parallel connection of resistors, each connected in series with a switch, wherein the resistance values of the series string of resistors vary according to a geometric progression with a common ratio substantially equal to about ½.
22. The circuit of claim 15 , wherein the trimmable current mirror further comprises:
a plurality of current sources;
a plurality of switches; and
an offset resistor,
wherein the current sources, switches and offset resistor are connected in an H-bridge.
23. The circuit of claim 15 , wherein one of the load resistors comprises a non-trimmable resistor that is sized to correspond to about ½ the maximum resistance value that can be reached by the trimmable resistor.
24. The circuit of claim 12 , wherein one of the load resistors comprises a non-trimmable resistor that is sized to correspond to about ½ the maximum resistance value that can be reached by the trimmable resistor.
25. The circuit of claim 12 , further comprising an active cascode circuit, the active cascode circuit comprising: a second pass transistor having a first node, a second node and a control node, the first node and second node connected in series between the second end of the second load resistor and the second current node of the current mirror; and an amplifier having a negative input, a positive input and an output, the positive input of the amplifier connected to the first current node of the current mirror, the negative input of the amplifier connected to the second current node of the current mirror, and output of the amplifier connected to the control node of the second pass transistor.