Granted Patent B2

US 7,307,467 · App. 11/380,799 · Granted Dec 11, 2007

Abstract

Claims (31)

1. A voltage divider device, comprising:

a double gate field effect transistor (FET) having a first gate and a second gate disposed at opposite sides of a body region;

an input voltage coupled between said first and second gates; and

an output voltage taken from at least one of a source of said FET and a drain of said FET, with said source and drain having opposite polarity types and coupled to one another;

wherein said output voltage represents a divided voltage with respect to said input voltage.

2. The device of claim 1 , wherein said FET is a planar, double gate device with said source and drain formed above said second gate, and said first gate formed above said source and drain.

3. The device of claim 1 , wherein said FET comprises a double gate finFET.

4. The device of claim 3 , wherein said first and second gates are of opposite polarity types.

5. The device of claim 1 , wherein a leakage current path through said FET is defined from said first gate, through a first gate oxide to one of said source and drain, through a common conductive path therebetween, to the other of said source and drain, through a second gate oxide and to said second gate.

6. The device of claim 1 , wherein at least one of said first and second gates have selectively variable areas.

7. A voltage divider device, comprising:

a double gate field effect transistor (FET) having a first gate and a second gate disposed at opposite sides of a body region;

an input voltage coupled across said first and second gates;

an output voltage taken from at least one of a source of said FET and a drain of said FET;

wherein said output voltage represents a divided voltage with respect to said input voltage; and

a plurality of double gate FETs configured in a stack arrangement, with a first terminal of an input voltage source coupled to a first gate of a first double gate FET, a second gate of said first double gate FET coupled to a first gate of a second double gate FET, and a second gate of a final double gate FET coupled to a second terminal of said input voltage source.

8. A voltage divider device, comprising:

a double gate field effect transistor (FET) having a first gate and a second gate disposed at opposite sides of a body region;

an input voltage coupled across said first and second gates; and

an output voltage taken from at least one of a source of said FET and a drain of said FET;

wherein said output voltage represents a divided voltage with respect to said input voltage; and

wherein said input voltage comprises output terminals of a differential amplifier, and said divided output voltage represents the common mode voltage of said differential amplifier.

9. A method for implementing an oxide leakage based voltage divider network, the method comprising:

coupling an input voltage across first and second gates of a double gate field effect transistor (FET), said first gate and second gates disposed at opposite sides of a body region; and

taking an output voltage from at least one of a source of said FET and a drain of said FET;

wherein said output voltage represents a divided voltage with respect to said input voltage;

wherein said source and drain are of opposite polarity types; and

a leakage current path through said FET is defined from said first gate, through a first gate oxide to one of said source and drain, through a common conductive path therebetween, to the other of said source and drain, through a second gate oxide and to said second gate.

10. The method of claim 9 , wherein said FET is a planar, double gate device with said source and drain formed above said second gate, and said first gate formed above said source and drain.

11. The method of claim 9 , wherein said FET comprises a double gate finFET.

12. The method of claim 9 , wherein said first and second gates are of opposite polarity types.

Assignments (6)