IP Library Granted Patent US 7,638,362
Granted Patent B2
US 7,638,362 · App. 11/382,347 · Granted Dec 29, 2009

Memory module with improved mechanical strength of chips

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Quick Facts
Patent No.
US 7,638,362
App. No.
11/382,347
Granted
Dec 29, 2009
Kind
B2
Abstract

A memory module of the present invention has a memory core chip for storing information, an interface chip for controlling data input/output, an interposer chip for transmitting/receiving data to/from the outside, and an external connection terminal provided in closest proximity to the interposer chip. A heat dissipating plate is provided in closest proximity to the interface chip. The interposer chip has a substrate made of a semiconductor material that is similar to the memory core chip, a land for holding the external connection terminal, a wire connected to the external connection terminal, and an insulating film for insulating the wire. The land, wire, and insulating film are integrally formed on one surface of the interposer chip.

Claims (27)

1. A method of manufacturing a memory module having a memory core chip for storing information, an interface chip for controlling data input/output to/from said memory core chip, and an interposer chip for transmitting/receiving the data between said interface chip and an outside, said method comprising the steps of:

adhering a support directly to a surface of said interface chip opposite to a surface on which a bump is formed;

subsequently placing said memory core chip on the surface of said interface chip on which the bump is formed, and thermo-compression bonding the bumps of said interface chip and said memory core chip to each other; and

placing said interposer chip on said memory core chip, and thermo-compression bonding the bumps of said memory core chip and said interposer chip to each other, wherein said support holds said interface chip, said memory core chip and said interposer chip at said thermo-compression bonding steps.

2. The method of manufacturing a memory module according to claim 1 , further comprising the step of encapsulating side surfaces of said interface chip, said memory core chip, and said interposer chip with a resin after thermo-compression bonding the bumps of said memory core chip and said interposer chip to each other.

3. The method of manufacturing a memory module according to claim 1 , further comprising the steps of:

adhering a plurality of said interface chips to said support in said step of adhering a support directly to a surface of said interface chip opposite to a surface on which a bump is formed;

encapsulating side surfaces of laminated chips including said interface chips, said memory core chip, and said interposer chip, after the step of thermo-compression bonding the bumps of said memory core chip and said interposer chip; and

cutting said support corresponding to said laminated chips encapsulated with the resin.

4. The method of manufacturing a memory module according to claim 2 , further comprising the step of mounting an external connection terminal in closest proximity to said interposer chip for electrically connecting to the outside after the step of encapsulating with a resin.

5. The method of manufacturing a memory module according to claim 3 , further comprising the step of mounting an external connection terminal in closest proximity to said interposer chip for electrically connecting to the outside after the step of encapsulating with a resin.

6. The method of manufacturing a memory module according to claim 1 , wherein said support is made of a metal plate.

7. The method of manufacturing a memory module according to claim 6 , wherein said support is a lead frame.

8. A method of manufacturing a memory module comprising;

preparing for a plurality of memory core chips;

preparing for an interface chip to control data transfer to/from each of the memory core chips, wherein the interface chip has a first surface and a second surface which is opposite to the first surface;

preparing for an interposer chip to transfer the data between the interface chip and an outside of the memory module;

adhering a lead frame plate directly to the first surface of the interface chip;

disposing the plurality of the memory core chips over the second surface of the interface chip after adhering the lead frame plate to the interface chip, and connecting the plurality of memory core chips and the interface chip by using thermo-compression bonding; and

subsequently disposing the interposer chip over the plurality of the memory core chips such that the interposer chip is directly connected to one of the plurality of memory core chips, and thermo-compression bonding between the interposer chip and the memory core chip which is directly connected to the interposer chip.

9. The method of manufacturing a memory module according to claim 8 , wherein each of the memory core chips comprises a plurality of bumps for thermo-compression bonding on a surface of each of the memory core chips.

10. The method of manufacturing a memory module according to claim 8 , further comprising the step of encapsulating side surfaces of the interface chip, the plurality of memory core chips, and the interposer chip with a resin after thermo-compression bonding between the memory core chip and the interposer chip.

11. The method of manufacturing a memory module according to claim 8 , further comprising;

forming a plurality of external connection terminals over a surface of the interposer chip at an opposite side to which the memory core chip is connected.

12. The method of manufacturing a memory module according to claim 11 , wherein the external connection terminals are solder balls.

13. The method of manufacturing a memory module according to claim 8 , wherein the lead frame plate is made of a metal.

14. The method of manufacturing a memory module according to claim 13 , wherein a size of the lead frame plate is larger than a size of the interposer chip when viewed from a surface of the interposer chip at an opposite side to which the memory core chip is connected.

Assignments (10)
RELEASE OF SECURITY INTEREST Recorded Nov 12, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
Reel/Frame 051028/0001 →
RELEASE OF SECURITY INTEREST Recorded Oct 9, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050937/0001 →
RELEASE OF SECURITY INTEREST Recorded Aug 23, 2018
From: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 047243/0001 →
SECURITY INTEREST Recorded Jul 13, 2018
From: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 047540/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REPLACE ERRONEOUSLY FILED PATENT #7358718 WITH THE CORRECT PATENT #7358178 PREVIOUSLY RECORDED ON REEL 038669 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST. Recorded Jun 8, 2017
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 043079/0001 →
PATENT SECURITY AGREEMENT Recorded Jun 2, 2016
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
Reel/Frame 038954/0001 →
SECURITY INTEREST Recorded May 12, 2016
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 038669/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 9, 2014
From: ELPIDA MEMORY, INC.
To: MICRON TECHNOLOGY, INC.
Reel/Frame 032645/0422 →
CORRECTIVE ASSIGNMENT TO CORRECT THE FIRST INVENTORS NAME FROM MASAAKI ISHINO TO MASAKAZU ISHINO PREVIOUSLY RECORDED ON REEL 017591 FRAME 0896. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Aug 28, 2006
From: ISHINO, MASAKAZU; IKEDA, HIROAKI
To: ELPIDA MEMORY, INC.
Reel/Frame 018177/0834 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 9, 2006
From: ISHINO, MASAAKI; IKEDA, HIROAKI
To: ELPIDA MEMORY, INC.
Reel/Frame 017591/0896 →