Semiconductor device including substrate and upper plate having reduced warpage
View Patent ↗A semiconductor device includes a lower substrate having at least one wiring pattern formed of a plurality of wirings, a semiconductor chip positioned above the lower substrate and electrically connected to the wirings, an intermediate member which seals the semiconductor chip in columnar form and substantially, and an upper plate which substantially covers a whole upper surface of the intermediate member. A thermal expansion coefficient of the upper plate and a thermal expansion coefficient of the lower substrate are set substantially identical.
1. A semiconductor device comprising:
a silicon substrate having at least one wiring pattern formed of a plurality of wirings;
a semiconductor chip positioned above the silicon substrate and electrically connected to the wirings;
an intermediate member which seals the semiconductor chip; and
an upper plate which substantially covers a whole upper surface of the intermediate member,
wherein a thermal expansion coefficient of the upper plate is substantially identical to a thermal expansion coefficient of the silicon substrate, and
wherein the thermal expansion coefficient of the silicon substrate and the thermal expansion coefficient of the upper plate are less than or equal to half a thermal expansion coefficient of the intermediate member.
2. The semiconductor device according to claim 1 , wherein thicknesses of the silicon substrate and the upper plate are substantially identical to each other.
3. The semiconductor device according to claim 2 , further comprising a plurality of semiconductor chips positioned above the silicon substrate.
4. The semiconductor device according to claim 3 , wherein the semiconductor chips are electrically connected to the wirings in accordance with a flip-chip system.
5. The semiconductor device according to claim 1 , further comprising a plurality of semiconductor chips positioned above the silicon substrate.
6. The semiconductor device according to claim 5 , wherein the semiconductor chips are electrically connected to the wirings in accordance with a flip-chip system.