Semiconductor device with a SiGe layer having uniaxial lattice strain
View Patent ↗A semiconductor device includes a MIS transistor. The device includes a buried insulating film formed in one part of a substrate, the buried insulating film being elongated in a gate-width direction and shortened in a gate-length direction of the MIS transistor. A first semiconductor layer is formed on the buried insulating film and has uniaxial lattice strain. A second semiconductor layer covers both sides of the buried insulating film and both sides of the first semiconductor layer, the sides being opposite in the gate-length direction. A gate electrode is formed on the first semiconductor layer with a gate insulating film being formed between the gate electrode and the first semiconductor layer. A source region and a drain region are formed in the second semiconductor layer.
1. A semiconductor device, comprising:
a gate for a Metal-Insulator Semiconductor (MIS) transistor on a support substrate;
a buried insulating film formed in one part of the substrate, the buried insulating film being longer in a gate-width direction than in a gate-length direction of the gate for the MIS transistor;
a first semiconductor layer of strained SiGe formed on the buried insulating film and having lattice strain in the gate-width direction and lattice strain relaxed in the gate-length direction;
a second semiconductor layer covering both sides of the buried insulating film and both sides of the first semiconductor layer, said sides being opposite in the gate-length direction;
a gate electrode for the MIS transistor formed on the first semiconductor layer with a gate insulating film being formed between the gate electrode and the first semiconductor layer; and
a source region and a drain region for the MIS transistor which are formed in the second semiconductor layer,
wherein the second semiconductor layer is an Si layer.
2. The semiconductor device according to claim 1 , wherein a depletion-inhibiting layer of a conductivity type opposite to a conductivity type of the source and drain regions is formed in a bottom region of the source and drain regions.
3. The semiconductor device according to claim 1 , wherein an extension region having a smaller junction depth than the first semiconductor layer is formed on sides of the source and drain regions which contact the first semiconductor layer.
4. The semiconductor device according to claim 3 , wherein an insulating sidewall is formed on sides of the gate electrode which oppose each other in the gate-length direction, and the extension region is formed beneath the insulating sidewall.
5. The semiconductor device according to claim 1 , wherein the second semiconductor layer is a layer epitaxially grown from the support substrate, and the second semiconductor layer is doped with impurities for forming the source and drain regions.
6. The semiconductor device according to claim 1 , wherein W≦2L, where W is a distance the first semiconductor layer and buried insulating film extend in the gate-width direction and L is a distance the first semiconductor layer and buried insulating film extend in the gate-length direction.