IP Library Granted Patent US 7,477,520
Granted Patent B2
US 7,477,520 · App. 11/391,450 · Granted Jan 13, 2009

Memory module

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Quick Facts
Patent No.
US 7,477,520
App. No.
11/391,450
Granted
Jan 13, 2009
Kind
B2
Abstract

In a memory module, a plurality of semiconductor memory packages are arranged and mounted on a module board, and a control semiconductor package is disposed in a central region of the arrangement of the semiconductor memory packages, and mounted on the module board. A control semiconductor radiator thermally connected to the control semiconductor package, and a semiconductor memory radiator thermally connected to the plurality of memory packages are disposed without being thermally connected to each other in relation to a direction in which the semiconductor memory packages are arranged.

Claims (32)

1. A memory module having a plurality of semiconductor memory packages arranged and mounted on a module board, the module comprising:

a control semiconductor package disposed in a central region of the arrangement of said semiconductor memory packages and mounted on said module board, and

a control semiconductor radiator thermally connected to said control semiconductor package, and a semiconductor memory radiator thermally connected to said plurality of semiconductor memory packages, wherein said control semiconductor radiator and said semiconductor memory radiator are disposed without being thermally connected to each other in a direction in which said semiconductor memory packages are arranged;

wherein the control semiconductor package and the plurality of semiconductor memory packages are mounted on a same side of said module board.

2. The memory module according to claim 1 , wherein a multi-layered semiconductor memory package stacked in a plurality of layers is used as said semiconductor memory package.

3. The memory module according to claim 2 , wherein the multi-layered semiconductor memory package comprises a plurality of memory chips.

4. The memory module according to claim 1 , wherein:

said control semiconductor radiator and said semiconductor memory radiator are constituted of different members, and

a gap is formed between said control semiconductor radiator and said semiconductor memory radiator in the direction in which said semiconductor memory packages are arranged to provide a non thermally connected part.

5. The memory module according to claim 4 , wherein said control semiconductor radiator and said semiconductor memory radiator connected to said control semiconductor package and said semiconductor memory package mounted on the same side of said module board are mounted such that their respective projection planes deviate from each other.

6. The semiconductor module according to claim 5 , comprising a notch recess formed in a central region of said semiconductor memory radiator, wherein said control semiconductor radiator is disposed within a projection plane of said notch recess.

7. The memory module according to claim 1 , wherein:

said control semiconductor radiator and said semiconductor memory radiator are constituted of the same member, and

a non thermally connected part is defined between said control semiconductor radiator and said semiconductor memory radiator in the direction in which said semiconductor memory packages are arranged.

8. The memory module according to claim 7 , wherein said non thermally connected part is formed of a slit extending in a direction which intersects the direction in which said semiconductor memory packages are arranged.

9. The memory module according to claim 1 , wherein:

said control semiconductor package has a heatproof temperature that is higher than the allowable heatproof temperature of said semiconductor memory package, and

said control semiconductor radiator is provided with radiation fins.

10. The memory module according to claim 9 , wherein said radiation fins provided on said control semiconductor radiator can be ventilated in any of front, rear, left and right directions.

11. The memory module according to claim 1 , wherein each of said control semiconductor radiator and said semiconductor memory radiator is provided with radiation fins along a wind direction.

12. The memory module according to claim 1 , wherein said plurality of semiconductor memory packages are arranged in a straight line.

13. A memory module comprising:

a module board,

a control semiconductor package mounted on a first surface of said module board,

a plurality of semiconductor memory packages mounted on the first surface of said module board and a plurality of semiconductor memory packages mounted on a second surface of said module board wherein said second surface opposes said first surface, and

a control semiconductor radiator thermally connected to said control semiconductor package, and a semiconductor memory radiator thermally connected to said plurality of semiconductor memory packages, wherein said control semiconductor radiator and said semiconductor memory radiator are disposed without being thermally connected to each other;

wherein at least one of the plurality of semiconductor memory packages mounted on the first surface of said module board and the plurality of semiconductor memory packages mounted on the second surface of said module board are disposed on the same surface of the module board as the control semiconductor package; and

wherein said control semiconductor package is disposed in a central region of the arrangement of said semiconductor memory packages.

14. The memory module according to claim 13 , wherein said plurality of semiconductor memory packages are arranged in a line on the first and second surfaces, respectively.

15. The memory module according to claim 14 , wherein said control semiconductor radiator and said semiconductor memory radiator are disposed such that their respective projection planes in the each surfaces deviate from each other.

16. The memory module according to claim 15 , comprising a notch recess formed in a central region of said semiconductor memory radiator, wherein said control semiconductor radiator is disposed within a projection plane of said notch recess.

17. The memory module according to claim 13 , wherein said control semiconductor radiator and said semiconductor memory radiator are constituted of different members.

Assignments (9)
RELEASE OF SECURITY INTEREST Recorded Nov 12, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
Reel/Frame 051028/0001 →
RELEASE OF SECURITY INTEREST Recorded Oct 9, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050937/0001 →
RELEASE OF SECURITY INTEREST Recorded Aug 23, 2018
From: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 047243/0001 →
SECURITY INTEREST Recorded Jul 13, 2018
From: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 047540/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REPLACE ERRONEOUSLY FILED PATENT #7358718 WITH THE CORRECT PATENT #7358178 PREVIOUSLY RECORDED ON REEL 038669 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST. Recorded Jun 8, 2017
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 043079/0001 →
PATENT SECURITY AGREEMENT Recorded Jun 2, 2016
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
Reel/Frame 038954/0001 →
SECURITY INTEREST Recorded May 12, 2016
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 038669/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 9, 2014
From: ELPIDA MEMORY, INC.
To: MICRON TECHNOLOGY, INC.
Reel/Frame 032645/0422 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 22, 2006
From: SHIBAMOTO, MASANORI; HISANO, NAE
To: ELPIDA MEMORY, INC.
Reel/Frame 018030/0257 →