High efficiency and/or high power density wide bandgap transistors
View Patent ↗Field effect transistors having a power density of greater than 40 W/mm when operated at a frequency of at least 4 GHz are provided. The power density of at least 40 W/mm may be provided at a drain voltage of 135 V. Transistors with greater than 60% PAE and a power density of at least 5 W/mm when operated at 10 GHz at drain biases from 28 V to 48 V are also provided.
1. A field effect transistor, comprising:
a Group III-nitride channel layer;
a gate contact on the Group III-nitride channel layer and configured to modulate a conductivity of the channel layer when a voltage is applied to the gate contact, the gate contact having a length configured to permit modulation of the conductivity of the channel layer at frequencies exceeding 1 GHz;
source and drain contacts on the Group III-nitride channel layer;
an insulating layer on the gate contact; and
a field plate on the insulating layer and electrically coupled to the source contact, wherein the field effect transistor exhibits a power density of greater than 40 W/mm under continuous wave or pulsed operation at a frequency of at least 4 GHz.
2. The field effect transistor of claim 1 , further comprising a Group III-nitride barrier layer on the channel layer, wherein the gate contact is on the barrier layer, and the barrier layer and the channel layer cooperatively induce a two-dimensional electron gas in the channel layer near an interface between the barrier layer and the channel layer.
3. The field effect transistor of claim 2 , wherein the barrier layer comprises a first barrier sublayer on the channel layer and a second barrier sublayer on the first barrier sublayer, the first barrier sublayer comprising AlN and the second barrier sublayer comprising Al x Ga 1-x N, wherein 0.15≦x≦0.45.
4. The field effect transistor of claim 3 , wherein the first barrier sublayer has a thickness of about 0 to about 4 nm and the second barrier sublayer has a thickness of about 10 to about 50 nm.
5. The field effect transistor of claim 1 , wherein the channel layer comprises a first channel sublayer and a second channel sublayer on the first channel sublayer, the first channel sublayer comprising GaN and having a concentration of Fe dopants of at least about 1×10 17 /cm 3 , the second channel sublayer comprising GaN and having a concentration of Fe dopants therein that decreases with distance from the first channel sublayer.
6. The field effect transistor of claim 1 , wherein the field plate comprises an upper field plate, the field effect transistor further comprising:
a spacer layer on the barrier layer; and
a lower field plate electrically connected to the gate and extending across the spacer layer from a drain side of the gate contact toward the drain contact by a distance L FD1 , wherein the upper field plate extends from a drain side edge of the lower field plate towards the drain contact by a distance L FD2 , and wherein L FD1 +L FD2 is about 1.0-2.5 μm.
7. The field effect transistor of claim 6 , wherein L FD1 is about 0.5 μm and L FD2 is about 1.2 μm.
8. The field effect transistor of claim 6 , wherein the lower field plate also extends across the spacer layer toward the source contact by a distance of from about 0 μm to about 0.5 μm.
9. The field effect transistor of claim 6 , wherein the spacer layer comprises SiN.
10. The field effect transistor of claim 1 , wherein the power density of at least 40 W/mm is provided at a drain voltage of 135 V.
11. The field effect transistor of claim 1 , wherein the field effect transistor has a power added efficiency greater than 50%.
12. A field effect transistor having a power density of greater than 40 W/mm under continuous wave or pulsed operation at a frequency of at least 4 GHz.
13. The field effect transistor of claim 12 , wherein the power density of at least 40 W/mm is provided at a drain voltage of 135 V.
14. The field effect transistor of claim 12 , wherein the field effect transistor has a power added efficiency greater than 50%.
15. A field effect transistor, comprising:
a Group III-nitride channel layer;
a gate contact on the Group III-nitride channel layer and configured to modulate a conductivity of the channel layer when a voltage is applied to the gate contact, the gate contact having a length configured to permit modulation of the conductivity of the channel layer at frequencies exceeding 1 GHz;
source and drain contacts on the Group III-nitride channel layer;
an insulating layer on the gate contact; and
a field plate on the insulating layer and electrically coupled to the source contact, wherein the field effect transistor exhibits a power density of greater than 5 W/mm and power added efficiency greater than 60% under continuous wave or pulsed operation at a frequency of at least 10 GHz.
16. The field effect transistor of claim 15 , further comprising a Group III-nitride barrier layer on the channel layer, wherein the gate contact is on the barrier layer, and the barrier layer and the channel layer cooperatively induce a two-dimensional electron gas in the channel layer near an interface between the barrier layer and the channel layer.
17. The field effect transistor of claim 16 , wherein the barrier layer comprises a first barrier sublayer on the channel layer and a second barrier sublayer on the first barrier sublayer, the first barrier sublayer comprising AlN and the second barrier sublayer comprising Al x Ga 1-x N, wherein 0.15≦x≦0.45.
18. The field effect transistor of claim 17 , wherein the first barrier sublayer has a thickness of about 0 to about 4 nm and the second barrier sublayer has a thickness of about 10 to about 50 nm.
19. The field effect transistor of claim 15 , wherein the channel layer comprises a first channel sublayer and a second channel sublayer on the first channel sublayer, the first channel sublayer comprising GaN and having a concentration of Fe dopants of at least about 1×10 17 /cm 3 , the second channel sublayer comprising GaN and having a concentration of Fe dopants therein that decreases with distance from the first channel sublayer.
20. The field effect transistor of claim 15 , wherein the field plate comprises an upper field plate, the field effect transistor further comprising:
a spacer layer on the barrier layer; and
a lower field plate electrically connected to the gate and extending across the spacer layer from a drain side edge of the gate contact toward the drain contact by a distance L FD1 , wherein the upper field plate extends from a drain side edge of the lower field plate towards the drain contact by a distance L FD2 , and wherein L FD1 +L FD2 is about 0.3-1.0 μm.
21. The field effect transistor of claim 20 , wherein L FD1 is about 0.25 μm and L FD2 is about 0.3 μm.
22. The field effect transistor of claim 20 , wherein the lower field plate also extends across the spacer layer toward the source contact by a distance of from about 0 μm to about 0.5 μm.
23. The field effect transistor of claim 20 , wherein the spacer layer comprises SiN.
24. A field effect transistor having a power density of greater than 5 W/mm and a power added efficiency greater than 60% when operated under continuous wave or pulsed operation in Class C mode at a frequency of at least 10 GHz.
25. The field effect transistor of claim 24 , wherein the power density of greater than 5 W/mm is provided at a drain voltage of at least 28 V.
26. The field effect transistor of claim 24 , wherein the field effect transistor has a power density of greater than 7 W/mm when operated in Class C mode at a frequency of at least 10 GHz.
27. The field effect transistor of claim 26 , wherein the power density of greater than 7 W/mm is provided at a drain voltage of at least 38 V.
28. The field effect transistor of claim 24 , wherein the field effect transistor has a power density of greater than 10 W/mm when operated in Class C mode at a frequency of at least 10 GHz.
29. The field effect transistor of claim 28 , wherein the power density of greater than 10 W/mm is provided at a drain voltage of at least 48 V.