IP Library Granted Patent US 7,095,641
Granted Patent B1
US 7,095,641 · App. 11/393,336 · Granted Aug 22, 2006

Content addressable memory (CAM) devices having priority class detectors therein that perform local encoding of match line signals

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Quick Facts
Patent No.
US 7,095,641
App. No.
11/393,336
Granted
Aug 22, 2006
Kind
B1
Abstract

Content addressable memory devices may include a priority encoder therein and a first tier of CAM arrays arranged side-by-side relative to each other, on a first side of the priority encoder. A priority class detector is also provided for efficiently communicating match information that is generated during a search operation. The priority class detector passes match information from a selected priority class of rows in a selected one of the CAM arrays in the first tier to the priority encoder. This operation to pass match information is performed in response to detecting a match in the selected priority class when a search operation is performed. The priority class detector performs operations to locally encode match lines associated with a respective CAM array by priority class. These match lines are associated with a plurality of consecutive rows or consecutive pairs of rows that are arranged in a repeating priority class sequence comprising different priority classes. The priority class sequence may be an alternating priority class sequence, with each physically even row (or even pair of rows) in a CAM array being associated with one priority class and each physically odd row (or odd pair of rows) in a CAM array being associated within another priority class. Alternative priority class sequences may also be provided.

Claims (12)

1. A content addressable memory (CAM) device, comprising:

a CAM array having entries therein that are arranged by priority class so that a plurality of consecutive entries or consecutive pairs of entries in said CAM array are arranged in a repeating priority class sequence comprising different priority classes.

2. The CAM device of claim 1 , wherein the plurality of consecutive entries or consecutive pairs of entries are arranged by alternating even and odd priority class.

3. A method of operating a content addressable memory (CAM) device, comprising the steps of:

performing a search operation between data applied to a CAM array and data entries therein to thereby detect a plurality of matching entries from different priority classes, with each matching entry being separated from another matching entry by an entry in a different priority class;

selectively identifying matches in a highest priority class containing at least one match; and

encoding the identified matches in the highest priority class into an address of a highest priority match within the highest priority class.

4. The method of claim 3 , wherein a plurality of consecutive rows in the CAM array contain entries arranged in a repeating priority class sequence.

5. A content addressable memory (CAM) device, comprising:

a pair of CAM arrays; and

a priority class detector electrically coupled to match lines in said pair of CAM arrays, said priority class detector comprising an N-to-1 priority class selection circuit, where N is a positive integer greater than one.

6. The CAM device of claim 5 , wherein each of said pair of CAM arrays has entries therein that are arranged by priority class so that a plurality of consecutive entries or consecutive pairs of entries in each of said pair of CAM arrays are arranged in a repeating priority class sequence comprising different priority classes.

Assignments (10)
CORRECTIVE ASSIGNMENT TO CORRECT THE EXECUTION DATE PREVIOUSLY RECORDED AT REEL: 047196 FRAME: 0097. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER. Recorded Mar 6, 2019
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 048555/0510 →
MERGER Recorded Oct 4, 2018
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 047196/0097 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS Recorded Feb 3, 2017
From: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
To: BROADCOM CORPORATION
Reel/Frame 041712/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 1, 2017
From: BROADCOM CORPORATION
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 041706/0001 →
PATENT SECURITY AGREEMENT Recorded Feb 11, 2016
From: BROADCOM CORPORATION
To: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
Reel/Frame 037806/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 16, 2015
From: NETLOGIC I LLC
To: BROADCOM CORPORATION
Reel/Frame 035443/0763 →
CHANGE OF NAME Recorded Apr 16, 2015
From: NETLOGIC MICROSYSTEMS, INC.
To: NETLOGIC I LLC
Reel/Frame 035443/0824 →
RELEASE OF SECURITY INTEREST Recorded Aug 30, 2011
From: SILICON VALLEY BANK
To: NETLOGIC MICROSYSTEMS, INC.; NETLOGIC MICROSYSTEMS INTERNATIONAL LIMITED; NETLOGIC MICROSYSTEMS CAYMANS LIMITED
Reel/Frame 026830/0141 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 21, 2009
From: INTEGRATED DEVICE TECHNOLOGY, INC.
To: NETLOGIC MICROSYSTEMS, INC.
Reel/Frame 022980/0624 →
SECURITY AGREEMENT Recorded Jul 17, 2009
From: NETLOGIC MICROSYSTEMS, INC.; NETLOGIC MICROSYSTEMS INTERNATIONAL LIMITED; NETLOGIC MICROSYSTEMS CAYMANS LIMITED
To: SILICON VALLEY BANK
Reel/Frame 022973/0710 →