Methods for erasing memory devices and multi-level programming memory device
A memory includes a first charge storage region spaced apart from a second charge storage region by an isolation region. Techniques for erasing a memory are provided in which electrons are Fowler-Nordheim (FN) tunneled out of at least one of the charge storage regions into a substrate to erase the at least one charge storage region of the memory. Other techniques are provided for programming a single charge storage region at multiple different levels or states.
1 . A method, comprising:
providing a memory comprising a first charge storage region spaced apart from a second charge storage region by an isolation region, wherein the charge storage regions comprise silicon rich nitride; and
Fowler-Nordheim (FN) tunneling electrons out of at least one of the charge storage regions into the substrate to erase the at least one charge storage region.
2 . A method according to claim 1 , wherein the memory further comprises a substrate and a gate, and wherein Fowler-Nordheim (FN) tunneling comprises:
grounding the substrate;
applying a voltage to the gate to push electrons from the at least one of the charge storage regions into the substrate.
4 . A method according to claim 1 , wherein the charge storage regions are physically and electrically separated by the isolation region disposed between the charge storage regions.
5 . A semiconductor device, comprising:
a substrate;
an isolation region;
a first charge storage region comprising silicon rich nitride;
a second charge storage region comprising silicon rich nitride, wherein the second charge storage region is spaced apart from the first charge storage region by the isolation region; and
a gate,
wherein at least one of the charge storage regions is configured to be erased by injecting electrons into the substrate from the at least one of the charge storage regions by grounding the substrate and applying a voltage to the gate to inject electrons from at least one of the charge storage regions into the substrate.
6 . A semiconductor device according to claim 5 , wherein the charge storage regions are physically and electrically separated by the isolation region disposed between the charge storage regions.
7 . A method, comprising:
providing a memory comprising a first charge storage region spaced apart from a second charge storage region by an isolation region, wherein the charge storage regions comprise polysilicon; and
Fowler-Nordheim (FN) tunneling electrons out of at least one of the charge storage regions into the substrate to erase the at least one charge storage region.
8 . A method according to claim 7 , wherein the memory further comprises a substrate and a gate, and wherein Fowler-Nordheim (FN) tunneling comprises:
grounding the substrate;
applying a voltage to the gate to push electrons from the at least one of the charge storage regions into the substrate.
9 . A method according to claim 7 , wherein the charge storage regions are physically and electrically separated by the isolation region disposed between the charge storage regions.
10 . A semiconductor device, comprising:
a substrate;
an isolation region;
a first charge storage region comprising polysilicon;
a second charge storage region comprising polysilicon, wherein the second charge storage region is spaced apart from the first charge storage region by the isolation region; and
a gate,
wherein at least one of the charge storage regions is configured to be erased by injecting electrons into the substrate from the at least one of the charge storage regions by grounding the substrate and applying a voltage to the gate to inject electrons from at least one of the charge storage regions into the substrate.
11 . A semiconductor device according to claim 10 , wherein the charge storage regions are physically and electrically separated by the isolation region disposed between the charge storage regions.
12 . A semiconductor device, comprising:
a substrate;
an isolation region;
a first charge storage region comprising silicon rich nitride, wherein the first charge storage region is configured to store a first bit and a second bit;
a second charge storage region comprising silicon rich nitride, wherein the second charge storage region is spaced apart from the first charge storage region by the isolation region, wherein the first charge storage region is configured to store a first complimentary bit 1 and a second complimentary bit 1 , wherein the isolation region is configured to prevent disturbance of a second threshold voltage of the first and second complimentary bit 1 when the first and second bits are programmed, respectively.
13 . A semiconductor device according to claim 12 , wherein the charge storage regions are physically and electrically separated by the isolation region disposed between the charge storage regions.
14 . A semiconductor device according to claim 12 , wherein a threshold voltage (V T ) window between the first charge storage region and the second charge storage region is approximately 4.5 volts or more.
15 . A semiconductor device according to claim 12 , wherein the first charge storage region is programmable at multiple states with the first threshold voltage (V T ) between zero and five volts, while the second threshold voltage (V T ) at the second charge storage region remains at approximately zero volts.