Data storing method of dynamic RAM and semiconductor memory device
View Patent ↗When a DRAM enters an operation mode in which only a data storing operation is performed, a check bit for error detection and correction for plural data is generated and stored. Refresh operation is performed in a refresh cycle which is made long within an allowable range of an error occurrence by an error correcting operation using the check bit. Before the DRAM returns to the normal operation mode from the data holding operation mode, an error bit is corrected by using the data and the check bit.
1. A semiconductor integrated circuit device comprising:
a memory circuit having a normal operation mode for data reading and writing, and a data retention mode; and
a data retention control circuit activated when the memory circuit enters the data retention mode, to perform a first operation of reading plural data stored in the memory circuit and generating and storing a check bit for error detection and correction, and activated when the memory circuit returns from the data retention mode to the normal operation mode, to perform a second operation of reading stored data and the stored check bit, correcting an error bit in the data, and writing corrected data into the memory circuit,
wherein in at least one refresh cycle of a refresh operation in the data retention mode, memory cells of the memory circuit are refreshed but an operation of error detection and correction is not performed and the refresh cycle is extended in an ECC correctable range.
2. The semiconductor integrated circuit device according to claim 1 , wherein the data retention control circuit includes a refresh cycle setting circuit that sets the length of refresh cycles.
3. The semiconductor integrated circuit device according to claim 2 , wherein the refresh cycle setting circuit adjusts the length of refresh cycles in accordance with temperature of the semiconductor integrated circuit device.
4. The semiconductor integrated circuit device according to claim 2 , wherein the refresh cycle setting circuit includes a cell leak monitor that sets refresh cycles longer than refresh cycles of the normal operation mode.