Semiconductor structure and fabrication thereof
View Patent ↗A method for fabricating a semiconductor structure is described. A substrate is provided, having thereon a gate structure and a spacer on the sidewall of the gate structure and having therein an S/D extension region beside the gate structure. An opening is formed in the substrate beside the spacer, and then an S/D region is formed in or on the substrate at the bottom of the opening. A metal silicide layer is formed on the S/D region and the gate structure, and then a stress layer is formed over the substrate.
1. A method for fabricating a semiconductor structure, comprising:
providing a substrate having thereon a gate structure and a spacer on a sidewall of the gate structure and having therein an S/D extension region beside the gate structure;
forming an opening in the substrate beside the spacer;
forming an S/D region in or on the substrate at bottom of the opening;
forming a metal silicide layer on the S/D region and the gate structure; and
forming a stress layer over the substrate and filling the opening, wherein the stress layer has a sufficient thickness to at least fill up the opening.
2. The method of claim 1 , wherein the step of forming the opening comprises:
forming over the substrate a patterned photoresist layer exposing the substrate beside the spacer;
etching and removing a portion of the exposed substrate using the patterned photoresist layer and the spacer as a mask; and
removing the patterned photoresist layer.
3. The method of claim 2 , wherein the etching comprises isotropic etching, anisotropic etching or tapered etching.
4. The method of claim 1 , wherein the step of forming the metal isotropic etching, anisotropic etching or tapered etching.
5. The method of claim 1 , wherein the step of forming the S/D region comprises an ion implantation process using the spacer and the gate structure as a mask.
6. The method of claim 1 , wherein the step of forming the S/D region comprises a selective epitaxy growth (SEG) process with in-situ doping.
7. The method of claim 1 , wherein the stress layer is a compressive stress layer or a tensile stress layer.
8. The method of claim 1 , wherein the opening has a depth of about 100-1000 Å.
9. A method for fabricating a semiconductor structure, comprising:
providing a substrate having a first and a second gate structures thereon;
forming a first S/D extension region of a first conductivity type in the substrate beside the first gate structure, and forming a second S/D extension region of a second conductivity type in the substrate beside the second gate structure;
forming a first spacer on a sidewall of the first gate structure, and forming a second spacer on a sidewall of the second gate structure;
forming an opening in the substrate beside the first spacer;
forming a first S/D region of the first conductivity type in or on the substrate at bottom of the opening to form a first MOS transistor of the first conductivity type, and forming a second S/D region of the second conductivity type in the substrate beside the second spacer to form a second MOS transistor of the second conductivity type; and
forming a first stress layer over the first MOS transistor and filling the opening, and forming a second stress layer over the second MOS transistor, wherein the first stress layer has a sufficient thickness to at least fill up the opening.
10. The method of claim 9 , further comprising forming a metal silicide layer on the first and the second S/D regions and the first and the second gate structures.
11. The method of claim 10 , wherein the step of forming the metal silicide layer comprises a salicide process.
12. The method of claim 9 , wherein the step of forming the opening comprises:
forming over the substrate a patterned photoresist layer exposing the substrate beside the first spacer;
etching and removing a portion of the exposed substrate using the patterned photoresist layer and the first spacer as a mask; and
removing the patterned photoresist layer.
13. The method of claim 12 , wherein the etching comprises isotropic etching, anisotropic etching or tapered etching.
14. The method of claim 9 , wherein the step of forming the first S/D region comprises an ion implantation process of the first conductivity type using the first spacer and the first gate structure as a mask.
15. The method of claim 9 , wherein the step of forming the first S/D region comprises a selective epitaxy growth (SEG) process with in-situ doping.
16. The method of claim 9 , wherein the step of forming the second S/D region comprises an ion implantation process of the second conductivity type using the second spacer and the second gate structure as a mask.
17. The method of claim 9 , wherein the step of forming the first S/D extension region comprises an ion implantation process of the first conductivity type using the first gate structure as a mask.
18. The method of claim 9 , wherein the step of forming the second S/D extension region comprises an ion implantation process of the second conductivity type using the second gate structure as a mask.
19. The method of claim 9 , wherein the opening has a depth of about 100-1000 Å.
20. The method of claim 9 , wherein the first conductivity type is P-type, the second conductivity type is N-type, the first stress layer is a compressive stress layer, and the second stress layer is a tensile stress layer.
21. The method of claim 9 , wherein the first conductivity type is N-type and the second conductivity type is P-type, the first stress layer is a tensile stress layer, and the second stress layer is a compressive stress layer.