Reducing DQ pin capacitance in a memory device
A system and method to operate an electronic device, such as a memory chip, with a data driver circuit that is configured to reduce data pin (DQ) capacitance . In a driver circuit that is comprised of a set of ODT (On-Die Termination) legs and a set of non-ODT legs, a method allows selective activation and deactivation of tuning transistors in the ODT and non-ODT legs. During a default operational state of the electronic device (e.g., when no data read operation is taking place), the tuning transistors in the non-ODT legs may be maintained “turned off” or “disabled” to reduce DQ pin capacitance contributed by these tuning transistors had they been active during this default state. These non-ODT leg tuning transistors may be turned on, for example, when a data read operation is to be performed. Similarly, the tuning transistors in the ODT legs also may be selectively enabled/disabled to further control or reduce DQ pin capacitance as desired. The logic circuits disclosed to accomplish the reduction in DQ pin capacitance not only conserve the existing chip real estate, but also do not negatively affect the speed with which signals may be output from the electronic device.
1. A method of operating a memory device, comprising:
operating at least a portion of an output driver in said memory device as an on die termination (ODT); and
enabling at least one tuning transistor in a non-ODT portion of said output driver only during a data read operation involving said memory device.
2. The method of claim 1 , further comprising:
disabling said at least one tuning transistor in said non-ODT portion after conclusion of said data read operation.
3. The method of claim 1 , further comprising selectively performing one of the following:
disabling at least one tuning transistor in said ODT portion of said output driver during a first operational state of said output driver; and
enabling said at least one tuning transistor in said ODT portion of said output driver during a second operational state of said output driver.
4. A memory device, comprising:
a plurality of memory cells to store data; and
an I/O circuit configured to facilitate a data read/write operation from/to one or more of said plurality of memory cells, wherein said I/O circuit includes:
an output driver having an ODT (on die termination) portion and a non-ODT portion; and
a first gate circuit in said output driver coupled to said non-ODT portion and configured to maintain at least one tuning transistor in said non-ODT portion disabled during a default operational state of said memory device.
5. The memory device of claim 4 , wherein said first gate circuit is further configured to enable said at least one tuning transistor in said non-ODT portion only during a data read operation from said plurality of memory cells.
6. The memory device of claim 5 , wherein said default operational state relates to an absence of said data read operation.
7. The memory device of claim 4 , wherein said I/O circuit further includes:
a second gate circuit in said output driver coupled to said ODT portion and configured to maintain at least one tuning transistor in said ODT portion enabled during a first operational state of said output driver and disabled during a second operational state of said output driver.
8. The memory device of claim 7 , wherein said I/O circuit further includes:
an impedance calibration circuit configured to operate on said at least one tuning transistor in said non-ODT portion and said at least one tuning transistor in said ODT portion, wherein outputs of said impedance calibration circuit are applied to said at least one tuning transistor in said non-ODT portion via said first gate circuit and to said at least one tuning transistor in said ODT portion via said second gate circuit.
9. A system, comprising:
a processor;
a bus; and
a memory device coupled to said processor via said bus, wherein said memory device includes:
a plurality of memory cells to store data; and
an I/O circuit configured to facilitate a data read/write operation from/to one or more of said plurality of memory cells, wherein said I/O circuit includes:
an output driver having an ODT (on die termination) portion and a non-ODT portion; and
a first gate circuit in said output driver coupled to said non-ODT portion and configured to maintain at least one tuning transistor in said non-ODT portion disabled during a default operational state of said memory device.
10. The system of claim 9 , wherein said first gate circuit in said memory device is further configured to enable said at least one tuning transistor in said non-ODT portion only during a data read operation from said plurality of memory cells.
11. The system of claim 9 , wherein said I/O circuit in said memory device further includes:
a second gate circuit in said output driver coupled to said ODT portion and configured to maintain at least one tuning transistor in said ODT portion enabled during a first operational state of said output driver and disabled during a second operational state of said output driver.
12. The system of claim 11 , wherein said I/O circuit in said memory device further includes:
an impedance calibration circuit configured to operate on said at least one tuning transistor in said non-ODT portion and said at least one tuning transistor in said ODT portion, wherein outputs of said impedance calibration circuit are applied to said at least one tuning transistor in said non-ODT portion via said first gate circuit and to said at least one tuning transistor in said ODT portion via said second gate circuit.