IP Library Granted Patent US 7,875,513
Granted Patent B2
US 7,875,513 · App. 11/411,311 · Granted Jan 25, 2011

Self-aligned bipolar junction transistors

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Quick Facts
Patent No.
US 7,875,513
App. No.
11/411,311
Granted
Jan 25, 2011
Kind
B2
Abstract

A plurality of bipolar transistors are formed by forming a common conduction region, a plurality of control regions extending each in an own active areas on the common conduction region, a plurality of silicide protection strips, and at least one control contact region. Silicide regions are formed on the second conduction regions and the control contact region. The second conduction regions may be formed by selectively implanting a first conductivity type dopant areas on a first side of selected silicide protection strips. The control contact region is formed by selectively implanting an opposite conductivity type dopant on a second side of the selected silicide protection strips.

Claims (9)

1. A method comprising:

forming bitlines extending in a first direction;

forming an etch mask that defines openings for implanting a base contact, an emitter, and a source of a field effect transistor; and

using said mask to form silicide on said source, said emitter, and said base contact, said silicide on said emitter being centered on said emitter in the first direction.

2. The method of claim 1 including using said mask to define an opening for said source by forming a sidewall spacer on a gate electrode.

3. The method of claim 1 including forming a plurality of bipolar transistors, said bipolar transistors having a common collector.

4. The method of claim 1 including forming said mask for emitter and base contact implants such that the emitter and base contact implants do not need to be aligned.

5. The method of claim 1 including forming a silicide over said emitter, source, and base contact.

6. The method of claim 5 wherein said silicide over said emitter, base, contact, and source is aligned by way of said etched mask.

Assignments (10)
RELEASE OF SECURITY INTEREST Recorded Nov 12, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
Reel/Frame 051028/0001 →
RELEASE OF SECURITY INTEREST Recorded Oct 9, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050937/0001 →
RELEASE OF SECURITY INTEREST Recorded Aug 23, 2018
From: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 047243/0001 →
SECURITY INTEREST Recorded Jul 13, 2018
From: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 047540/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REPLACE ERRONEOUSLY FILED PATENT #7358718 WITH THE CORRECT PATENT #7358178 PREVIOUSLY RECORDED ON REEL 038669 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST. Recorded Jun 8, 2017
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 043079/0001 →
PATENT SECURITY AGREEMENT Recorded Jun 2, 2016
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
Reel/Frame 038954/0001 →
SECURITY INTEREST Recorded May 12, 2016
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 038669/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 17, 2012
From: INTEL CORPORATION
To: NUMONYX B.V.
Reel/Frame 028055/0625 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 18, 2011
From: NUMONYX B.V.
To: MICRON TECHNOLOGY, INC.
Reel/Frame 027075/0682 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 1, 2008
From: PELLIZZER, FABIO; BEZ, ROBERTO; ZULIANI, PAOLA; BENVENUTI, AUGUSTO
To: INTEL CORPORATION
Reel/Frame 020481/0187 →