Memory cell array with low resistance common source and high current drivability
View Patent ↗In the present resistive memory array, included are a substrate, a plurality of source regions in the substrate, and a conductor connecting the plurality of source regions, the conductor being positioned adjacent to the substrate to form, with the plurality of source regions, a common source. In one embodiment, the conductor is an elongated metal body of T-shaped cross-section. In another embodiment, the conductor is a plate-like metal body.
1. A semiconductor device comprising:
a substrate;
a plurality of spaced source regions in the substrate, the plurality of spaced source regions arranged in a column of source regions; and
an elongated conductor connecting the plurality of spaced source regions, the elongated conductor, along the length thereof, being positioned adjacent to the substrate to form, with the plurality of spaced source regions, a common source;
wherein the conductor includes a first elongated portion in contact with each of the plurality of source regions, and a second elongated portion connected to the first portion and spaced from the substrate, the second elongated portion being elongated in the same direction as the first elongated portion;
wherein the first portion is narrower in cross-sectional width than the cross-sectional width of each of the plurality of source regions.
2. The semiconductor device of claim 1 wherein the second portion is wider in cross-sectional width than the first portion.
3. The semiconductor device of claim 2 wherein the conductor is generally T-shaped in cross-section perpendicular to its length.
4. The semiconductor device of claim 3 wherein the conductor is substantially straight along its length.
5. The semiconductor device of claim 4 wherein the conductor is metal.
6. The semiconductor device of claim 5 and further comprising a drain region in the semiconductor substrate, and a gate, the common source, drain region and gate being parts of a transistor.
7. A semiconductor device comprising:
a substrate;
a plurality of spaced source regions in the substrate, the plurality of spaced source regions arranged in a column of source regions; and
an elongated conductor connecting the plurality of spaced source regions, the elongated conductor, along the length thereof, being positioned adjacent to the substrate to form, with the plurality of spaced source regions, a common source;
wherein the conductor includes a first portion in contact with each of the plurality of source regions, and a second portion connected to the first portion and spaced from the substrate;
a drain region in the semiconductor substrate, and a gate, the common source, drain region and gate being parts of a transistor;
wherein at least a part of the second portion overlies at least a portion of the gate of the transistor.
8. A semiconductor device comprising:
a substrate;
a plurality of spaced source regions in the substrate; and
an elongated conductor connecting the plurality of source regions, the elongated conductor, along the length thereof, being positioned adjacent to the substrate to form, with the plurality of source regions, a common source;
wherein the conductor is of plate-like configuration, the plate-like conductor comprising a first portion in contact with respective source regions of the plurality thereof, and a second portion connected to the first portion and spaced from the substrate; and
wherein the plate-like conductor defines an opening therethrough, and further comprising a resistive memory device over the substrate and communicating with the substrate through the opening in the plate-like opening.
9. The semiconductor device of claim 8 wherein the opening through the plate-like conductor is defined by the second portion thereof.
10. The semiconductor device of claim 9 and further comprising a diode in series with the resistive memory device.
11. A semiconductor device comprising:
a substrate;
a first plurality of spaced source regions in the substrate;
a second plurality of spaced source regions in the substrate;
a plate-like conductor comprising a first plurality of portions, one of the first plurality of portions connecting the first plurality of source regions and positioned on the substrate, another of the first plurality of portions connecting the second plurality of source regions and positioned on the substrate;
the plate-like conductor further comprising a second plurality of portions connecting the first plurality of portions, the second plurality of portions being spaced from the substrate
wherein the plate-like conductor defines an opening therethrough, and further comprising a resistive memory device over the substrate and communicating with the substrate through the opening in the plate-like conductor.
12. The semiconductor device of claim 11 and further comprising an isolation region between the first plurality of source regions and the second plurality of source regions.
13. The semiconductor device of claim 11 wherein the opening through the plate-like conductor is defined by a second portion thereof.
14. The semiconductor device of claim 11 and further comprising a diode in series with the resistive memory device.