Semiconductor device with reduced transistor breakdown voltage for preventing substrate junction currents
View Patent ↗A semiconductor device is provided which includes a gate electrode ( 30 ) provided on a semiconductor substrate ( 10 ), an oxide/nitride/oxide (ONO) film ( 18 ) that is formed between the gate electrode ( 30 ) and the semiconductor substrate ( 10 ) and has a charge storage region ( 14 ) under the gate electrode ( 30 ), and a bit line ( 28 ) that is buried in the semiconductor substrate ( 10 ) and includes a low concentration diffusion region ( 24 ), a high concentration diffusion region ( 22 ) that is formed in the center of the low concentration diffusion region ( 24 ) and has a higher impurity concentration than the low concentration region, a source region, and a drain region. The semiconductor device can improve the source-drain breakdown voltage of the transistor while suppressing fluctuation of electrical characteristics or junction current between the bit line ( 28 ) and the semiconductor substrate ( 10 ).
1. A semiconductor device comprising:
a gate electrode located above a channel region in a semiconductor substrate; an ONO film formed between the semiconductor substrate and the gate electrode;
multiple charge storage regions provided in the ONO film under the gate electrode and above the channel region; and
a bit line formed in the semiconductor substrate and adjoining the channel region, the bit line comprising a bit line region serving as both a source region and a drain region for storing and reading information stored in the multiple charge storage regions, the bit line region including a low concentration diffusion region and a high concentration diffusion region, wherein the high concentration region is provided at a center of the low concentration diffusion region and has a higher impurity concentration than the low concentration diffusion region and wherein the low concentration diffusion region is the only diffusion region that contacts side portions of the high concentration diffusion region.
2. The semiconductor device as claimed in claim 1 , wherein the bit line includes pocket implantation diffusion regions formed at both sides of the low concentration diffusion region.
3. The semiconductor device as claimed in claim 1 , further comprising a word line provided above the bit line and connected to the gate electrode at an upper side thereof.
4. The semiconductor device as claimed in claim 3 , further comprising sidewalls provided at sides of the gate electrode.
5. The semiconductor device as claimed in claim 1 , further comprising a silicided metal layer provided on the semiconductor substrate over the bit line and running continuously in a direction of a length of the bit line.