Memory voltage cycle adjustment
The present disclosure includes various method, device, system, and module embodiments for memory cycle voltage adjustment. One such method embodiment includes counting a number of process cycles performed on a first memory block in a memory device. This method embodiment also includes adjusting at least one program voltage, from an initial program voltage to an adjusted voltage, in response to the counted number of process cycles.
1. A method comprising;
counting a number of process cycles performed on a first memory block in a memory device; and
adjusting at least one program voltage, from an initial program voltage to an adjusted voltage, in response to the counted number of process cycles, wherein the at least one program voltage is a set of stepped voltage pulses having at least two different step up voltages.
2. The method of claim 1 wherein adjusting a number of program voltages is accomplished by decreasing each of the number of program voltages.
3. The method of claim 1 wherein adjusting a number of program voltages is accomplished by decreasing each of the number of program voltages as the counted number of process cycles for the memory block increases.
4. The method of claim 1 wherein adjusting a number of program voltages is accomplished by decreasing each of the number of program voltages periodically as the counted number of process cycles for the memory block increases past a number of process cycle count thresholds.
5. A method comprising;
counting a number of program/erase cycles performed on a first memory block in a memory device having a memory array comprising a plurality of memory blocks, each memory block having a plurality of memory cells arranged in rows that are coupled by word lines; and
adjusting a number of program voltages, from an initial program voltage, over time in response to the counted number of program/erase cycles, wherein the number of program voltages are a set of stepped voltage pulses having at least two different step up voltages.
6. The method of claim 5 wherein adjusting the number of program voltages is accomplished periodically based upon a number of program/erase cycle count thresholds.
7. The method of claim 5 wherein the number of program voltages are in arrange of 16-20V.
8. The method of claim 5 wherein the number of adjusted program voltages are in a range of 14-19V.
9. The method of claim 5 wherein adjusting a number of program voltages, from an initial program voltage, over time in response to the counted number of program/erase cycles is accomplished by decreasing at least one of the number of program voltages.
10. A method comprising;
counting a number of program/erase cycles performed on a first memory block in a memory device having a memory array comprising a plurality of memory blocks, each memory block having a plurality of memory cells arranged in rows that are coupled by word lines; and
decreasing each of a number of stepped program voltages having at least two different step up voltages, from an initial program voltage, in response to the count of program/erase cycles.
11. The method of claim 10 wherein decreasing each of a number of stepped program voltages having at least two different step up voltages, from an initial program voltage, in response to the counted number of program/erase cycles is accomplished by decreasing each of the number of program voltages by 0.6V.
12. The method of claim 10 wherein decreasing each of a number of stepped program voltages having at least two different step up voltages, from an initial program voltage, in response to the counted number of program/erase cycles is accomplished by decreasing each of a number of stepped program voltages as the count of program/erase cycles for the memory block increases.
13. The method of claim 10 wherein decreasing each of a number of stepped program voltages having at least two different step up voltages, from an initial program voltage, in response to the counted number of program/erase cycles is accomplished by decreasing each of a number of stepped program voltages as the count of program/erase cycles for the memory block increases, wherein an increase to a larger program voltage is greater than an increase to a smaller program voltage.
14. A non-volatile memory device comprising:
an array of non-volatile memory cells arranged in rows coupled by word lines and columns coupled by bit lines; and
control circuitry coupled to the array of non-volatile memory cells and adapted to execute a method for programming that includes:
generating an initial programming voltage, wherein the initial programming voltage is a set of stepped voltage pulses having at least two different step up voltages;
counting a quantity of program/erase cycles; and
decreasing the programming voltage based upon the quantity of program/erase cycles.
15. The device of claim 14 wherein the control circuitry is programmed to decrease the program voltage by a particular voltage amount each time the count reaches a predetermined quantity of program/erase cycles.
16. The device of claim 14 wherein the control circuitry is programmed to decrease the program voltage by a particular voltage amount each time the count reaches a quantity of 1,000 program/erase cycles.
17. The device of claim 14 wherein the control circuitry is programmed to decrease a first program voltage by a first voltage amount and a second program voltage by a second voltage amount.
18. The device of claim 14 wherein the control circuitry is programmed to decrease a first program voltage at a first time and a second program voltage at a second time.
19. The device of claim 14 wherein the control circuitry is programmed to decrease a first program voltage by a particular voltage amount when the count reaches a first predetermined quantity of program/erase cycles and decrease a second program voltage by a particular voltage amount when the count reaches a second predetermined quantity of program/erase cycles.
20. A non-volatile memory device comprising:
an array of non-volatile memory cells arranged in rows coupled by word lines and columns coupled by bit lines; and
control circuitry coupled to the array of non-volatile memory cells and adapted to execute a method for programming that includes;
generating an initial programming voltage, wherein the initial programming voltage is a set of stepped voltage pulses having at least two different step up voltages;
counting a quantity of program/erase cycles;
decreasing a first program voltage by a first voltage amount when the quantity of program/erase cycles reaches a first predetermined quantity of program/erase cycles; and
decreasing a second program voltage by a second voltage amount when the quantity of program/erase cycles reaches a second predetermined quantity of program/erase cycles.
21. The device of claim 20 wherein the first and second predetermined quantities of program/erase cycles are different.
22. The device of claim 20 wherein the first and second voltage amounts are different.
23. The device of claim 20 wherein the first and second predetermined quantities of program/erase cycles are different and the first and second voltage amounts are different.
24. The device of claim 20 wherein the first and second program voltages are pulsed program voltages, and wherein a step up voltage associated with the first program voltage is the same as a step up voltage associated with the second program voltage.
25. The device of claim 20 wherein the array of non-volatile memory cells is arranged in a NOR architecture.
26. A memory system comprising:
a processor for generating memory control signals;
a flash memory device coupled to the processor, the device comprising memory cell array arranged in rows and columns; and
control circuitry for controlling a number of program voltages during a program operation wherein:
the control circuitry is adapted to adjust at least one of the program voltages, from an initial program voltage to an adjusted program voltage in response to a cycle count; and
the at least one of the program voltages are a set of stepped voltage pulses having at least two different step up voltages.
27. The system of claim 26 wherein the control circuitry for controlling a number of program voltages during a program operation wherein the control circuitry is adapted to adjust at least one of the program voltages, from an initial program voltage to an adjusted program voltage in response to a program cycle count.
28. The system of claim 26 wherein the control circuitry for controlling a number of program voltages during a program operation wherein the control circuitry is adapted to adjust at least one of the program voltages, from an initial program voltage to an adjusted program voltage in response to a erase cycle count.
29. A memory module comprising:
a memory device comprising:
a memory cell array arranged in rows and columns;
control circuitry for controlling a number of program voltages to adjust at least one of the program voltages, from an initial program voltage to an adjusted program voltage in response to a cycle count, wherein the at least one of the program voltages is a set of stepped voltage pulses having at least two different step up voltages; and
a plurality of contacts configured to provide selective contact between the memory device and a host system.
30. The module of claim 29 and further including a memory controller coupled to the memory device for controlling operation of the memory device in response to the host system.
31. The module of claim 29 wherein the plurality of non-volatile memory cells are flash memory cells.