IP Library Granted Patent US 7,399,701
Granted Patent B2
US 7,399,701 · App. 11/417,044 · Granted Jul 15, 2008

Semiconductor device manufacturing method including forming a metal silicide layer on an indium-containing layer

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Quick Facts
Patent No.
US 7,399,701
App. No.
11/417,044
Granted
Jul 15, 2008
Kind
B2
Abstract

The present invention provides a semiconductor device manufacturing method of a semiconductor device having a contact plug, in which a contact hole formed by a surface portion of a high-concentration N-type diffusion layer formed on a semiconductor silicon substrate surface and an interlayer insulating film is implanted with indium ions at an energy ranging from 30 to 120 keV and an implantation amount ranging from 1.0×10 13 /cm 2 to 5.0×10 14 /cm 2 to grow an indium-containing layer on the surface portion of the high-concentration N-type diffusion layer at the bottom of the contact hole.

Claims (16)

1. A semiconductor device manufacturing method comprising the steps of:

(1) forming a high-concentration N-type diffusion layer on a surface of a semiconductor silicon substrate;

(2) forming an interlayer insulating film on the semiconductor silicon substrate with the high-concentration N-type diffusion layer;

(3) etching a predetermined position of the interlayer insulating film to form a contact hole reaching the high-concentration N-type diffusion layer;

(4) implanting a surface portion of the high-concentration N-type diffusion layer with indium ions at an energy ranging from 30 keV to 120 keV and an implantation amount ranging from 1.0×10 13 /cm 2 to 5.0×10 14 /cm 2 via the contact hole to grow an indium-containing layer at a bottom of the contact hole;

(5) annealing the semiconductor substrate after implanting the indium ions;

(6) depositing a metal by a chemical vapor deposition process at a temperature sufficient to expedite a reaction between the metal and the silicon substrate to form a metal silicide layer on the indium-containing layer formed at the bottom of the contact hole;

7 forming a barrier layer on an upper surface of the interlayer insulating film and an inner surface of the contact hole; and

8 forming a contact plug in the contact hole.

2. The semiconductor device manufacturing method according to claim 1 , wherein the metal suicide layer is of at least one selected from the group consisting of TiSi 2 , CoSi 2 , TaSi 2 , PtSi 2 and NiSi 2 .

3. The semiconductor device manufacturing method according to claim 2 , wherein an acceleration energy for implantation of the indium ions ranges from 40 keV to 100 keV.

4. The semiconductor device manufacturing method according to claim 3 , wherein the implantation amount ranges from 4.0×10 13 /cm 2 to 1.0×10 14 /cm 2 .

5. The semiconductor device manufacturing method according to claim 2 , wherein the implantation amount ranges from 4.0×10 13 /cm 2 to 1.0×10 14 /cm 2 .

6. The semiconductor device manufacturing method according to claim 1 , wherein an acceleration energy for implantation of the indium ions ranges from 40 keV to 100 keV.

7. The semiconductor device manufacturing method according to claim 6 , wherein the implantation amount ranges from 4.0×10 13 /cm 2 to 1.0×10 14 /cm 2 .

8. The semiconductor device manufacturing method according to claim 1 , wherein the implantation amount ranges from 4.0×10 13 /cm 2 to 1.0×10 14 /cm 2 .

Assignments (8)
RELEASE OF SECURITY INTEREST Recorded Nov 12, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
Reel/Frame 051028/0001 →
RELEASE OF SECURITY INTEREST Recorded Oct 9, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050937/0001 →
RELEASE OF SECURITY INTEREST Recorded Aug 23, 2018
From: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 047243/0001 →
SECURITY INTEREST Recorded Jul 13, 2018
From: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 047540/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REPLACE ERRONEOUSLY FILED PATENT #7358718 WITH THE CORRECT PATENT #7358178 PREVIOUSLY RECORDED ON REEL 038669 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST. Recorded Jun 8, 2017
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 043079/0001 →
PATENT SECURITY AGREEMENT Recorded Jun 2, 2016
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
Reel/Frame 038954/0001 →
SECURITY INTEREST Recorded May 12, 2016
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 038669/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 9, 2014
From: ELPIDA MEMORY, INC.
To: MICRON TECHNOLOGY, INC.
Reel/Frame 032645/0422 →