IP Library Granted Patent US 7,531,424
Granted Patent B1
US 7,531,424 · App. 11/417,737 · Granted May 12, 2009

Vacuum wafer-level packaging for SOI-MEMS devices

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 7,531,424
App. No.
11/417,737
Granted
May 12, 2009
Kind
B1
Abstract

A device and method for fabricating the device is disclosed. The device includes a substrate having an active layer disposed on a sacrificial layer. A trench is formed in the active layer to electrically isolate first and second regions in the active layer, and a non-conductive material is deposited on the substrate such that the non-conductive material fills the trench to form a substantially planar surface for support of further components of the device. In some cases, the non-conductive material fills only a portion of the trench sufficient to form the substantially planar surface. The non-conductive material may include silicon nitride.

Claims (22)

1. A method of fabricating a device, the method comprising the steps of:

forming a trench in an active layer of a silicon-on-insulator substrate having a sacrificial layer on which the active layer is disposed, the trench being configured to electrically isolate first and second regions of the active layer;

depositing a non-conductive material on the substrate such that the non-conductive material fills the trench to form a substantially planar support surface above the trench and the first and second regions of the active layer;

forming a MEMS device structure from the active layer in the first region;

forming a conductive interconnect line that crosses over the trench via the substantially planar support surface for an electrical connection with the MEMS device structure; and

bonding a cap wafer to the silicon-on-insulator substrate in a bonding area through which the conductive interconnect line passes, the bonding step forming an encapsulation region in which the MEMS device structure and the trench are entirely disposed.

2. The method of claim 1 , wherein the depositing step fills a portion of the trench sufficient to form the substantially planar surface.

3. The method of claim 1 , wherein the non-conductive material comprises silicon nitride.

4. The method of claim 1 , wherein the non-conductive material comprises low-stress silicon nitride.

5. The method of claim 1 , further comprising the step of forming an insulator disposed on the interconnect line to accommodate a bonding encapsulation material.

6. The method of claim 1 , further comprising the step of forming a wire bond pad disposed on the second region of the active layer and connected to the respective device structure via the conductive interconnect line such that the wire bond pad is disposed outside of the encapsulation region.

7. A method of fabricating a device, the method comprising the steps of:

forming a trench in an active layer of a silicon-on-insulator substrate having a sacrificial layer on which the active layer is disposed, the trench being configured to electrically isolate first and second regions of the active layer;

depositing a non-conductive material on the substrate such that the non-conductive material sufficiently fills the trench;

forming a MEMS device structure from the active layer in the first region;

forming a conductive interconnect line that crosses over the trench for an electrical connection with the MEMS device structure; and

bonding a cap wafer to the silicon-on-insulator substrate in a bonding area through which the conductive interconnect line passes, the bonding step forming an encapsulation region in which the MEMS device structure and the trench are entirely disposed;

wherein the non-conductive material sufficiently fills the trench to structurally support the conductive interconnect line across the trench.

8. The method of claim 7 , wherein the depositing step fills a portion of the trench sufficient to form a substantially planar surface.

9. The method of claim 7 , wherein the non-conductive material comprises silicon nitride.

10. The method of claim 7 , wherein the non-conductive material comprises low-stress silicon nitride.

11. The method of claim 7 , further comprising the step of forming a wire bond pad disposed on the second region of the active layer and connected to the respective device structure via the conductive interconnect line such that the wire bond pad is disposed outside of the encapsulation region.

Assignments (10)
RELEASE OF SECURITY INTEREST Recorded Mar 14, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 060894/0437 →
RELEASE OF SECURITY INTEREST Recorded Mar 11, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059363/0001 →
RELEASE OF SECURITY INTEREST Recorded Mar 10, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059863/0400 →
SECURITY INTEREST Recorded Jun 4, 2021
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
Reel/Frame 057935/0474 →
SECURITY INTEREST Recorded Dec 24, 2020
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 055671/0612 →
SECURITY INTEREST Recorded Jun 5, 2020
From: MICROCHIP TECHNOLOGY INC.; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION
Reel/Frame 053468/0705 →
RELEASE OF SECURITY INTEREST Recorded May 30, 2020
From: JPMORGAN CHASE BANK, N.A, AS ADMINISTRATIVE AGENT
To: MICROCHIP TECHNOLOGY INC.; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 053466/0011 →
SECURITY INTEREST Recorded Apr 24, 2020
From: MICROCHIP TECHNOLOGY INC.; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 053311/0305 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 4, 2013
From: DISCERA, INC.
To: MICREL, INCORPORATED
Reel/Frame 031346/0685 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 28, 2006
From: PAI, MINFAN
To: DISCERA, INC.
Reel/Frame 018019/0784 →