Amplifier circuit with bias stage for controlling a common mode output voltage of the gain stage during device power-up
View Patent ↗An improved amplifier circuit is provided herein with a gain stage and a bias stage, which may be switchably connected to the gain stage during power-up operations. The bias stage reduces a power-up time associated with the gain stage, while minimizing current consumption in the next amplifier stage and improving battery life. For example, during power-up, the bias stage may enable the output voltage of the gain stage to gradually rise from a ground potential to a desired common mode level in a highly controlled and predictable manner. By preventing “glitches” in the output voltage, the bias stage eliminates the need for inserting switches in the signal path between the output nodes of the gain stage and input nodes of the next amplifier stage.
1. An amplifier circuit, comprising:
a pair of transistors directly electrically connected between a power supply and first nodes of a respective pair of capacitors, wherein a gate terminal of each of the pair of transistors is mutually coupled to each other and to second nodes of the respective pair of capacitors; and
a bias circuit adapted to supply a first bias voltage above a ground supply to the first nodes and to supply a second bias voltage below the power supply to the second nodes.
2. The amplifier circuit as recited in claim 1 , wherein the first bias voltage is supplied prior to differential signals being applied to the first nodes.
3. The amplifier circuit as recited in claim 1 , wherein the first bias voltage is terminated prior to differential signals being applied to the first nodes.
4. The amplifier circuit as recited in claim 1 , wherein the first bias voltage is supplied after the power supply is applied to and thereafter removed from the second nodes.
5. The amplifier circuit as recited in claim 1 , wherein the first bias voltage is approximately equal to a gate-to-source voltage of a transistor above the ground supply.
6. The amplifier circuit as recited in claim 1 , further comprising a feedback circuit coupled to place a common mode voltage of a pair of differential signal upon the mutually coupled gate terminals.
7. The amplifier circuit as recited in claim 6 , wherein the first bias voltage is less than the common mode voltage.
8. The amplifier circuit as recited in claim 6 , wherein the second bias voltage is approximately equal to the common mode voltage.
9. An amplifier circuit, comprising:
a gain stage having a pair of common mode feedback transistors coupled in parallel between a power supply node and a pair of compensation capacitors, such that mutually coupled gate terminals of the common mode feedback transistors are connected to positive terminals of the compensation capacitors; and
a bias stage switchably connected to the gain stage for supplying a first bias current to negative terminals of the compensation capacitors and a second bias current to the positive terminals of the compensation capacitors, wherein the bias stage comprises a current mirror coupled for supplying the first bias current to a first pair of switches, which are closed for charging the negative terminals of the compensation capacitors to a first voltage level.
10. The amplifier circuit as recited in claim 9 , wherein the first and second bias currents are supplied prior to applying a differential signal to the compensation capacitors.
11. The amplifier circuit as recited in claim 9 , wherein the bias stage further comprises a diode-connected transistor coupled between the power supply node and the current mirror, wherein a gate terminal of the diode connected transistor is switchably connected to the positive terminals of the compensation capacitors through a second pair of switches, which are closed for charging the positive terminals of the compensation capacitors to a second voltage level.
12. The amplifier circuit as recited in claim 11 , wherein the bias stage reduces a potential difference between the positive and negative terminals of the compensation capacitors to reduce an amount of time needed to fully charge the compensation capacitors during a power-up operation.
13. The amplifier circuit as recited in claim 12 , wherein an amplitude of the first bias current is selected so that: the first voltage level will be greater than a ground potential; and
the second voltage level will be approximately equal to a common mode feedback voltage supplied to the mutually coupled gate terminals of the common mode feedback transistors.
14. The amplifier circuit as recited in claim 9 , wherein no switches are coupled between output nodes of the gain stage and input nodes of a following amplifier or buffer stage.