Transmission network having an optical receiver that utilizes dual power pins and a single status pin to lower power consumption, lower manufacturing cost, and increase transmission efficiency
View Patent ↗A communication network is provided for interconnecting a network of digital systems, such as multimedia devices. Each node of the communication network may include a receiver and a transmitter. The receiver and transmitter of each node can be an optical receiver and transmitter. The optical receiver is preferably powered by two power supply pins, each providing different supply amounts. An activity detector within the receiver can be powered from a first supply amount, and the signal path of the optical receiver can be supplied from a second supply amount greater than the first supply amount. The first supply amount is provided at all times, and the second supply amount is only provided if activity is detected. A voltage regulator which provides the first supply amount can be beneficially embodied on the same integrated circuit as a network interface to reduce the manufacturing cost of the network. By powering the activity detector separate from the signal path, power down and power up (normal) operating states are envisioned for reducing power consumption and increasing longevity of the optical receiver and transmitter.
1. A receiver circuit, comprising:
a first power supply pin capable of supplying a first supply amount exclusively to a first portion of the receiver circuit, wherein the first portion comprises an activity detector circuit having a photodetector coupled to a comparator and a timer;
a second power supply pin capable of selectively supplying a second supply amount, greater than the first supply amount, exclusively to a second portion of the receiver circuit; and
a status pin for conveying a status signal to enable the second supply amount to the second portion whenever an incoming signal is detected by the first portion.
2. The receiver as recited in claim 1 , wherein the first supply amount is supplied continuously to only the first portion of the receiver circuit.
3. The receiver as recited in claim 1 , wherein the first supply amount comprises a first current amount, and wherein the second supply amount comprises a second current amount.
4. The receiver as recited in claim 1 , wherein the second supply amount is greater than 100 times the first supply amount.
5. The receiver as recited in claim 1 , wherein the second supply amount is supplied to only the second portion of the receive circuit after the incoming signal is detected.
6. The receiver as recited in claim 1 , wherein the second portion comprises a data input port and a data processor.
7. A communication network, comprising:
a receiver comprising an activity detector and a data processor, wherein the activity detector is coupled to receive a first power supply pin and the data processor is coupled to receive a second power supply pin;
a voltage reference generator for producing a first supply amount forwarded to the first power supply pin; and
a network interface coupled to the receiver and comprising logic for enabling a second supply amount forwarded to the second power supply pin only when the activity detector detects a signal applied to the receiver.
8. The communication network as recited in claim 7 , wherein the activity detector and the data processor are coupled to a photodetector.
9. The communication network as recited in claim 7 , wherein the receiver further comprises a status pin for producing a status signal to indicate when the activity detector detects the signal applied to the receiver.
10. The communication network as recited in claim 7 , wherein a status pin upon the receiver and network interface is linked for transmitting an address between the receiver and the network interface.
11. The communication network as recited in claim 7 , wherein a status pin upon the receiver and network interface is linked for transmitting data between the receiver and the network interface.
12. The communication network as recited in claim 11 , wherein the address and the data are separated by a write bit or a read bit of opposite logic states.
13. The communication network as recited in claim 7 , wherein a status pin upon the receiver and network interface is linked for transmitting a voltage approximately half a logic one value from the network interface to signal the start of an address transfer from the network interface.
14. The communication network as recited in claim 7 , wherein the network interface comprises the voltage reference generator upon a single monolithic substrate and the network interface, except for the voltage reference generator and the logic, is coupled to receive the second supply amount.
15. The communication network as recited in claim 7 , wherein the voltage reference generator comprises an amplifier having one input coupled to receive a reference voltage and the other input coupled to receive a voltage-divided output from the amplifier.
16. The communication network as recited in claim 15 , wherein the amplifier comprises a comparator.
17. The communication network as recited in claim 15 , wherein the amplifier receives power through a resistor coupled to a battery.
18. The communication network as recited in claim 7 , wherein the receiver is coupled to receive a command signal sent from a downstream network interface linked to the receiver via a network, and wherein the downstream network interface computes whether a downstream receiver coupled to the downstream network interface receives an incoming signal that is greater than or less than a predetermined value and for sending a power down or power up value, respectively, as at least a part of the command signal over the network to the receiver.
19. The communication network as recited in claim 18 , further comprising a driver circuit coupled to receive the command signal via the receiver and for applying the driver circuit output to a transmitter for changing the output from the driver circuit depending on whether the command signal comprises a power down or power up value.
20. The communication network as recited in claim 19 , further comprising a calibration test fixture coupled to the receiver and the transmitter for varying the driver circuit output to where the receiver receives an incoming message from the calibration test fixture when the transmitter output power is equal to a predetermined value.
21. The communication network as recited in claim 7 , wherein the activity detector and the data processor are embodied upon a single, first monolithic substrate separate from the network interface embodied upon a single, second monolithic substrate.