Automatic test equipment operating architecture
View Patent ↗An integrated circuit testing device, such as an ATE, configured with an architecture comprising a distinct software layer and a distinct hardware layer with an interface for tester abstraction providing a communication conduit between the software layer and the hardware layer. The software layer communicates in device under test terms whereas the hardware layer communicates in the terms of the testing apparatus. Various communication interface points are provided to the software and hardware layers, as well as the interface for tester abstraction.
1. An automatic testing equipment comprising:
a runtime software layer comprising indications of integrated circuit device under test pin information, the runtime software layer communicating in device under test terms;
a runtime hardware layer comprising indications of integrated circuit automatic test equipment instrument information, the runtime hardware layer communicating in automatic test equipment hardware terms; and
an interface for translating the device under test terms from the runtime software layer to the automatic test equipment hardware terms of the runtime hardware layer, wherein said runtime hardware layer is operable to send a testing signal to a device under test (DUT) and responsive thereto receive a response from said DUT.
2. The automatic testing equipment of claim 1 further comprising:
a common access port in communication with the runtime software layer.
3. The automatic testing equipment of claim 1 further comprising:
a hardware register interface in communication with the runtime hardware layer.
4. The automatic testing equipment of claim 1 , wherein the indications of integrated circuit device under test pin information further comprise a device under test pin type.
5. The automatic testing equipment of claim 4 , wherein the device under test pin type is selected from the group consisting of clock, data bus, power supply, input and output.
6. The automatic testing equipment of claim 1 , wherein the device under test terms further comprise:
a voltage level;
a test pattern; and
a test pattern timing.
7. The automatic testing equipment of claim 1 , wherein the indications of integrated circuit automatic test equipment instrument information further comprise:
an instrument slot designator; and
an instrument pin designator.
8. The automatic testing equipment of claim 1 , wherein the automatic test equipment hardware terms further comprise:
a hardware register location; and
a hardware register content.
9. A method of controlling an automatic test equipment (ATE), said method comprising:
receiving a block definition operable to define a layout of an integrated circuit (IC) device under test (DUT) by mapping said DUT to said ATE, wherein said block definition is in said DUT terms;
translating said block definition to instrument terms of said ATE; and
programming said ATE in accordance with said instrument terms of said ATE, wherein said programming is operable to test a functionality of said IC DUT.
10. The method as described in claim 9 further comprising:
parsing said block definition to form a parsed block definition; and
in response to said parsing, resolving said parsed block definition to form said DUT terms.
11. The method as described in claim 9 further comprising:
in response to said programming, applying a stimulus to said IC DUT;
receiving a response from said IC DUT; and
comparing said response with an expected response.
12. The method as described in claim 9 , wherein said block definition comprises said IC DUT pin information.
13. The method as described in claim 12 , wherein said IC DUT pin information comprises a DUT pin type.
14. The method as described in claim 9 , wherein said translating is operable to logically separate the architecture and control over said ATE.
15. A system of automatic testing equipment comprising:
an automatic test equipment (ATE) comprising:
a runtime software layer comprising indications of integrated circuit device under test pin information, the runtime software layer communicating in device under test terms;
a runtime hardware layer comprising indications of integrated circuit automatic test equipment instrument information, the runtime hardware layer communicating in automatic test equipment hardware terms; and
an interface for translating the device under test terms from the runtime software layer to the automatic test equipment hardware terms of the runtime hardware layer, wherein said runtime hardware layer is operable to send a testing signal to a device under test (DUT) and responsive thereto receive a response from said DUT; and said device under test (DUT) coupled to said ATE.
16. The system as described in claim 15 , wherein said ATE is operable to send a plurality of stimulus signals to said DUT, and wherein said ATE is further operable to receive a plurality responses from said DUT that are responsive to said plurality of stimulus signals, and wherein said ATE is further operable to compare said plurality of responses to expected responses from said DUT.
17. The automatic testing equipment of claim 15 further comprising:
a hardware register interface in communication with the runtime hardware layer.
18. The automatic testing equipment of claim 15 , wherein the indications of integrated circuit device under test pin information further comprise a device under test pin type.
19. The automatic testing equipment of claim 18 , wherein the device under test pin type is selected from the group consisting of clock, data bus, power supply, input and output.
20. The automatic testing equipment of claim 15 , wherein the device under test terms further comprise:
a voltage level;
a test pattern; and
a test pattern timing.
21. The automatic testing equipment of claim 15 , wherein the indications of integrated circuit automatic test equipment instrument information further comprise:
an instrument slot designator; and an instrument pin designator.
22. The automatic testing equipment of claim 15 , wherein the automatic test equipment hardware terms further comprise:
a hardware register locations; and
a hardware register content.