IP Library Granted Patent US 7,332,935
Granted Patent B2
US 7,332,935 · App. 11/425,585 · Granted Feb 19, 2008

Driver with variable output voltage and current

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 7,332,935
App. No.
11/425,585
Granted
Feb 19, 2008
Kind
B2
Abstract

A driver circuit with variable output voltage and current. A source input terminal of the driver circuit may receive a source control signal. A voltage control circuit may drive one of the terminals of a first switch to a source voltage. If the source input terminal receives an asserted source control signal, the first switch is turned on and the voltage control circuit drives an output terminal of the driver circuit to the source voltage. A source current mirror may regulate a source current provided to the output terminal of the driver circuit. A sink input terminal of the driver circuit may receive a sink control signal. If the sink input terminal receives an asserted sink control signal, a second switch is turned on and the output terminal is driven to a sink voltage. A sink current mirror may regulate a sink current provided to output terminal of the driver circuit.

Claims (45)

1. A driver circuit comprising:

an output terminal;

a source input terminal configured to couple to a first switch and configured to receive a source control signal;

a voltage control circuit configured to drive one of the terminals of the first switch to a source voltage;

wherein, in response to receiving an asserted source control signal, the first switch is turned on and the voltage control circuit is operable to drive the output terminal of the driver circuit to the source voltage;

a source current mirror coupled to the first switch and configured to regulate a source current provided to the output terminal of the driver circuit when the first switch is turned on;

a sink input terminal configured to couple to a second switch and configured to receive a sink control signal, wherein, in response to receiving an asserted sink control signal, the second switch is turned on and the output terminal of the driver circuit is driven to a sink voltage; and

a sink current mirror coupled to the second switch and configured to regulate a sink current provided to output terminal of the driver circuit when the second switch is turned on.

2. The driver circuit of claim 1 , wherein the source current mirror is coupled between the first switch and a source current source, and wherein the sink current mirror is coupled between the output terminal of the driver circuit and the second switch, wherein the second switch is also coupled to a sink current source.

3. The driver circuit of claim 1 , wherein the voltage control circuit includes an amplifier, wherein a first input terminal of the amplifier is coupled to a reference voltage source and a second input terminal of the amplifier is coupled to one of the terminals of the first switch.

4. The driver circuit of claim 3 , wherein an output terminal of the amplifier is coupled to a gate terminal of a transistor, wherein the drain terminal of the transistor is coupled to the source current mirror, and the source terminal of the transistor is coupled to the first switch and the second input terminal of the amplifier, wherein the amplifier is operable to drive the transistor and maintain the source voltage at a voltage value associated with the reference voltage source.

5. The driver circuit of claim 1 , wherein, in response to receiving both a deasserted source control signal and a deasserted sink control signal, the first switch and the second switch are turned off and the driver circuit is configured to enter a tristate mode of operation.

6. The driver circuit of claim 1 , wherein, in response to receiving an asserted source control signal, the driver circuit is configured to enter a source mode of operation, wherein during the source mode of operation the driver circuit is operable to drive the output terminal to a high state.

7. The driver circuit of claim 1 , wherein, in response to receiving an asserted sink control signal, the driver circuit is configured to enter a sink mode of operation, wherein during the sink mode of operation the driver circuit is operable to drive the output terminal to a low state.

8. The driver circuit of claim 1 , wherein the source control signal and the sink control signal are independent control signals used for controlling the mode of operation of the driver circuit.

9. The driver circuit of claim 1 , wherein the source current mirror and the sink current mirror are operable to independently control the source current and the sink current, respectively, provided to the output terminal of the driver circuit.

10. The driver circuit of claim 1 , wherein the source voltage is lower than a voltage value associated with a supply voltage of the driver circuit.

11. The driver circuit of claim 1 , further comprising a second voltage control circuit configured to drive one of the terminals of the second switch to a sink voltage, wherein in response to receiving an asserted sink control signal, the second switch is turned on and the second voltage control circuit is operable to drive the output terminal of the driver circuit to the sink voltage.

12. The driver circuit of claim 1 , wherein the first switch and the second switch are configured as transistors.

13. A driver circuit comprising:

a first transistor;

a second transistor;

an output terminal;

a source input terminal coupled to the gate terminal of the first transistor, wherein the source terminal of the first transistor is coupled to the output terminal of the driver circuit;

a voltage control circuit coupled to the drain terminal of the first transistor, wherein the voltage control circuit is configured to drive the drain terminal of the first transistor to a source voltage;

a source current mirror coupled between the drain terminal of the first transistor and a source current source;

a sink input terminal coupled to the gate terminal of the second transistor, wherein the drain terminal of the second transistor is coupled to a sink current source; and

a sink current mirror coupled between the output terminal of the driver circuit and the source terminal of the second transistor.

14. The driver circuit of claim 13 , wherein the voltage control circuit includes an amplifier, wherein a first input terminal of the amplifier is coupled to a reference voltage source and a second input terminal of the amplifier is coupled to the drain terminals of the first transistor.

15. The driver circuit of claim 14 , wherein an output terminal of the amplifier is coupled to a gate terminal of a third transistor, wherein the drain terminal of the third transistor is coupled to the source current mirror, and the source terminal of the third transistor is coupled to the drain terminal of the first transistor and the second input terminal of the amplifier.

16. The driver circuit of claim 13 , wherein the source input terminal is configured to receive a source control signal, wherein, in response to receiving an asserted source control signal, the first transistor is turned on and the voltage control circuit is operable to drive the output terminal of the driver circuit to the source voltage.

17. The driver circuit of claim 16 , wherein the source current mirror is configured to regulate a source current provided to output terminal of the driver circuit when the first transistor is turned on.

18. The driver circuit of claim 13 , wherein the sink input terminal is configured to receive a sink control signal, wherein, in response to receiving an asserted sink control signal, the second transistor is turned on and the output terminal of the driver circuit is driven to a sink voltage.

19. The driver circuit of claim 18 , wherein the sink current mirror is configured to regulate a sink current provided to output terminal of the driver circuit when the second transistor is turned on.

20. A system comprising:

a driver control unit configured to generate a source control signal and a sink control signal; and

a driver circuit including:

an output terminal;

a source input terminal configured to couple to a first switch and configured to receive the source control signal;

a voltage control circuit configured to drive one of the terminals of the first switch to a source voltage;

wherein, in response to receiving an asserted source control signal, the first switch is turned on and the voltage control circuit is operable to drive the output terminal of the driver circuit to the source voltage;

a source current mirror coupled to the first switch and configured to regulate a source current provided to the output terminal of the driver circuit when the first switch is turned on;

a sink input terminal configured to couple to a second switch and configured to receive the sink control signal, wherein, in response to receiving an asserted sink control signal, the second switch is turned on and the output terminal of the driver circuit is driven to a sink voltage; and

a sink current mirror coupled to the second switch and configured to regulate a sink current provided to output terminal of the driver circuit when the second switch is turned on.

21. The system of claim 20 , coupled to a target device via a communication medium, wherein the driver circuit of the system is configured to drive the communication medium with either the source voltage or the sink voltage to communicate with the target device.

Assignments (10)
RELEASE OF SECURITY INTEREST Recorded Mar 14, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 060894/0437 →
RELEASE OF SECURITY INTEREST Recorded Mar 11, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059363/0001 →
RELEASE OF SECURITY INTEREST Recorded Mar 10, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059863/0400 →
SECURITY INTEREST Recorded Jun 4, 2021
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
Reel/Frame 057935/0474 →
SECURITY INTEREST Recorded Dec 24, 2020
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 055671/0612 →
SECURITY INTEREST Recorded Jun 5, 2020
From: MICROCHIP TECHNOLOGY INC.; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION
Reel/Frame 053468/0705 →
RELEASE OF SECURITY INTEREST Recorded May 30, 2020
From: JPMORGAN CHASE BANK, N.A, AS ADMINISTRATIVE AGENT
To: MICROCHIP TECHNOLOGY INC.; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 053466/0011 →
SECURITY INTEREST Recorded Apr 24, 2020
From: MICROCHIP TECHNOLOGY INC.; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 053311/0305 →
MERGER Recorded Dec 11, 2017
From: STANDARD MICROSYSTEMS CORPORATION
To: MICROCHIP TECHNOLOGY INCORPORATED
Reel/Frame 044824/0608 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 21, 2006
From: ILLEGEMS, PAUL F.; PULIJALA, SRINIVAS
To: STANDARD MICROSYSTEMS CORPORATION
Reel/Frame 017824/0381 →