IP Library Granted Patent US 7,361,957
Granted Patent B2
US 7,361,957 · App. 11/426,037 · Granted Apr 22, 2008

Device for electrostatic discharge protection and method of manufacturing the same

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Quick Facts
Patent No.
US 7,361,957
App. No.
11/426,037
Granted
Apr 22, 2008
Kind
B2
Abstract

The present invention relates to a device for electrostatic discharge protection (ESD). According to an embodiment of the present invention, a device for electrostatic discharge protection includes a semiconductor substrate, a plurality of field oxide films formed in predetermined regions on the semiconductor substrate, a gate formed in a predetermined region on the semiconductor substrate between the field oxide films, a well pick-up region formed in a predetermined region on the semiconductor substrate between the field oxide films, a source formed in a predetermined region on the semiconductor substrate between the field oxide film and the gate, a drain drift region formed in a predetermined region on the semiconductor substrate between the gate and the field oxide film, a drain active region of a concentration higher than that of the drain drift region, the drain active region being formed in the drain drift region, and an oxide film formed on the semiconductor substrate on a boundary of the drain drift region and the drain active region. Accordingly, the current concentrated on the surface of the device can be uniformly distributed over the entire device.

Claims (23)

1. A device for electrostatic discharge protection, comprising:

semiconductor substrate;

a plurality of field oxide films formed in predetermined regions on the semiconductor substrate;

a gate formed in a predetermined region on the semiconductor substrate between the field oxide films;

a well pick-up region formed in a predetermined region on the semiconductor substrate between the field oxide films;

a source formed in a predetermined region on the semiconductor substrate between the field oxide film and the gate;

drain drift region formed in a predetermined region on the semiconductor substrate between the gate and the field oxide film;

a drain active region of a concentration higher than that of the drain drift region, the drain active region being formed in the drain drift region; and

an oxide film formed only on a boundary of the drain drift region and the drain active region.

2. The device for electrostatic discharge protection as claimed in claim 1 , wherein the oxide film is formed not to be in contact with the gate.

3. The device for electrostatic discharge protection as claimed in claim 1 , wherein the well pick-up region, the source and the gate are applied with a ground voltage, and the drain active region is applied with a positive voltage.

4. A device for electrostatic discharge protection, comprising:

a semiconductor substrate;

a plurality of field oxide films formed in predetermined regions on the semiconductor substrate;

a gate formed in a predetermined region on the semiconductor substrate between the field oxide films;

a well pick-up region formed in a predetermined region on the semiconductor substrate between the field oxide films;

a source drift region formed in a predetermined region on the semiconductor substrate between the field oxide film and the gate;

a source active region of a concentration higher than that of the source drift region, the source active region being formed within the source drift region;

a drain drift region formed in a predetermined region on the semiconductor substrate between the gate and the field oxide film;

a drain active region of a concentration higher than that of the drain drift region, the drain active region being formed in the drain drift region; and

an oxide film formed only on a boundary of the drain drift region and the drain active region.

5. The device for electrostatic discharge protection as claimed in claim 4 , wherein the oxide film is formed not to be in contact with the gate.

6. The device for electrostatic discharge protection as claimed in claim 4 , wherein the well pick-up region, the source active region and the gate applied with a ground voltage, and the drain active region is applied with a positive voltage.

Assignments (6)
CHANGE OF NAME Recorded Mar 12, 2024
From: KEY FOUNDRY CO., LTD.
To: SK KEYFOUNDRY INC.
Reel/Frame 066794/0290 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 3, 2020
From: MAGNACHIP SEMICONDUCTOR, LTD.
To: KEY FOUNDRY CO., LTD.
Reel/Frame 053703/0227 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 22, 2017
From: KIM, KIL HO; JUNG, YONG ICC
To: MAGNACHIP SEMICONDUCTOR, LTD.
Reel/Frame 041335/0995 →
CORRECTIVE ASSIGNMENT TO CORRECT THE RECEIVING PARTY ADDRESS PREVIOUSLY RECORDED AT REEL: 024563 FRAME: 0807. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE BY SECURED PARTY. Recorded Nov 25, 2014
From: US BANK NATIONAL ASSOCIATION
To: MAGNACHIP SEMICONDUCTOR LTD.
Reel/Frame 034469/0001 →
RELEASE OF SECURITY INTEREST Recorded Jun 22, 2010
From: U.S. BANK NATIONAL ASSOCIATION
To: MAGNACHIP SEMICONDUCTOR LTD.
Reel/Frame 024563/0807 →
AFTER-ACQUIRED INTELLECTUAL PROPERTY KUN-PLEDGE AGREEMENT Recorded Feb 18, 2009
From: MAGNACHIP SEMICONDUCTOR, LTD.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL TRUSTEE
Reel/Frame 022277/0133 →