IP Library Granted Patent US 7,655,969
Granted Patent B2
US 7,655,969 · App. 11/431,509 · Granted Feb 2, 2010

Semiconductor device having a cylindrical capacitor

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Quick Facts
Patent No.
US 7,655,969
App. No.
11/431,509
Granted
Feb 2, 2010
Kind
B2
Abstract

A DRAM device has a stacked capacitor including a first capacitor section received in a thick insulation film and a second capacitor section overlying the first capacitor section. A portion of the bottom electrode in the second capacitor section has a thickness larger than the thickness of another portion of the bottom electrode in the first capacitor section.

Claims (69)

1. A semiconductor device comprising:

a semiconductor substrate;

a first container insulation film overlying said semiconductor substrate;

a first capacitor section received in said first container insulation film and including a first bottom electrode having a first length, a first capacitor insulation film, and a first top electrode opposing said first bottom electrode with an intervention of said first capacitor insulation film; and

a second capacitor section overlying said first capacitor section and including a second bottom electrode having a second length extending from said first bottom electrode, a second capacitor insulation film extending from said first capacitor insulation film, and a second top electrode extending from said first top electrode and opposing said second bottom electrode with an intervention of said second capacitor insulation film, wherein,

a thickness of said second bottom electrode along an entirety of the second length is larger than a thickness of said first bottom electrode along an entirety of the first length.

2. The semiconductor device according to claim 1 , wherein,

said second bottom electrode is cylindrical,

said second capacitor insulation film is provided on both an inner cylindrical surface and an outer cylindrical surface of said second bottom electrode, and

said second top electrode opposes both the inner cylindrical surface and the outer cylindrical surface of said second bottom electrode.

3. The semiconductor device according to claim 1 , wherein,

said first bottom electrode is comprised of a first electrode film, and

said second bottom electrode is comprised of said first electrode film and a second electrode film provided on said first electrode film.

4. The semiconductor device according to claim 1 , wherein a bottom portion of said first bottom electrode is connected to a diffused region of said semiconductor substrate via a conductive plug.

5. A method for manufacturing a semiconductor device, comprising:

forming a first container insulation film overlying a semiconductor substrate;

forming a first cylindrical hole in said first container insulation film;

forming a cylindrical first conductive film on a surface of said first cylindrical hole;

forming a second container insulation film on said first container insulation film to fill said first cylindrical hole on said cylindrical first conductive film;

selectively etching said second container insulation film to form therein a second cylindrical hole to expose therethrough a top portion of said cylindrical first conductive film;

forming a cylindrical second conductive film on a surface of said second cylindrical hole to extend from said cylindrical first conductive film;

removing a portion of said second container insulation film outside said second cylindrical hole to thereby expose an outer surface of said second cylindrical conductive film;

forming a capacitor insulation film on an inner surface of said cylindrical first conductive film and inner and outer surfaces of said second cylindrical conductive film; and

forming a third conductive film opposing said cylindrical first and second conductive films with an intervention of said capacitor insulation film,

wherein said cylindrical second conductive film is formed with a thickness larger than a thickness of said cylindrical first conductive film, and

wherein the semiconductor device manufactured by the method comprises a structure as claimed in claim 1 .

6. The method according to claim 5 , wherein said first container insulation film includes a lower insulation film and an upper insulation film, and said upper insulation film acts as an etch stopper film during said selective etching of said second container insulation film.

7. A method for manufacturing a semiconductor device, comprising:

consecutively forming first and second container insulation films overlying a semiconductor substrate;

forming a cylindrical hole in said first and second container insulation films;

forming a cylindrical first conductive film on a surface of said cylindrical hole;

forming a filling insulation film filling said cylindrical hole up to a depth corresponding to a thickness of said first container insulation film;

forming a second cylindrical conductive film on an exposed inner surface of said cylindrical first conductive film;

removing said filling insulation film and said second container insulation film;

forming a capacitor insulation film on exposed inner and outer surfaces of said cylindrical first conductive film and on an inner surface of said cylindrical second conductive film; and

forming a third conductive film opposing said cylindrical first and second conductive films with an intervention of said capacitor insulation film,

wherein the semiconductor device manufactured by the method comprises a structure as claimed in claim 1 .

8. The semiconductor device according to claim 1 , wherein,

said second bottom electrode is cylindrical,

said first bottom electrode is cylindrical, and

a diameter of an inner surface of said first bottom electrode is greater than a diameter of an inner surface of said second bottom electrode.

9. A semiconductor device comprising:

a semiconductor substrate;

a first container insulation film overlying said semiconductor substrate;

a first bottom electrode having a first vertical length;

a first top electrode opposing said first bottom electrode along the first vertical length;

a first capacitor insulation film provided between said first bottom electrode and said first top electrode along the first vertical length,

said first bottom electrode, said first top electrode, and said first capacitor insulation defining a first capacitor section;

a second bottom electrode having a second vertical length extending from an end portion of said first bottom electrode;

a second top electrode extending from an end portion of said first top electrode, said second top electrode opposing said second bottom electrode along the second vertical length; and

a second capacitor insulation film extending from said first capacitor insulation film, said second capacitor insulation film provided between said second bottom electrode and said second top electrode along the second vertical length,

said second bottom electrode, said second top electrode and said second capacitor insulation film defining a second capacitor section overlying said first capacitor section,

wherein a thickness of said second bottom electrode along an entirety of the second vertical length is greater than a thickness of said first bottom electrode along an entirety of the first vertical length, and

wherein a horizontal width of said first top electrode along the entirety of the first length is greater than a horizontal width of said second top electrode along the entirety of the second length.

10. The semiconductor device according to claim 9 , wherein,

said second bottom electrode is cylindrical,

said first bottom electrode is cylindrical, and

a diameter of an inner surface of said first bottom electrode is greater than a diameter of an inner surface of said second bottom electrode.

11. The semiconductor device according to claim 9 , wherein,

said second bottom electrode is cylindrical,

said second capacitor insulation film is provided on both an inner cylindrical surface of said second bottom electrode and an outer cylindrical surface of said second bottom electrode, and

said second top electrode opposes both the inner cylindrical surface and the outer cylindrical surface of said second bottom electrode.

12. The semiconductor device according to claim 9 , wherein,

said first bottom electrode is comprised of a first electrode film, and

said second bottom electrode is comprised of said first electrode film and a second electrode film provided on said first electrode film.

13. The semiconductor device according to claim 9 , further comprising:

a diffused region of said semiconductor substrate; and

a conductive plug connected to said diffused region,

wherein a bottom portion of said first bottom electrode is connected to said diffused region.

Assignments (9)
RELEASE OF SECURITY INTEREST Recorded Nov 12, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
Reel/Frame 051028/0001 →
RELEASE OF SECURITY INTEREST Recorded Oct 9, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050937/0001 →
RELEASE OF SECURITY INTEREST Recorded Aug 23, 2018
From: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 047243/0001 →
SECURITY INTEREST Recorded Jul 13, 2018
From: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 047540/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REPLACE ERRONEOUSLY FILED PATENT #7358718 WITH THE CORRECT PATENT #7358178 PREVIOUSLY RECORDED ON REEL 038669 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST. Recorded Jun 8, 2017
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 043079/0001 →
PATENT SECURITY AGREEMENT Recorded Jun 2, 2016
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
Reel/Frame 038954/0001 →
SECURITY INTEREST Recorded May 12, 2016
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 038669/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 9, 2014
From: ELPIDA MEMORY, INC.
To: MICRON TECHNOLOGY, INC.
Reel/Frame 032645/0422 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 11, 2006
From: TAKAISHI, YOSHIHIRO
To: ELPIDA MEMORY, INC.
Reel/Frame 017886/0995 →