Method for forming fully silicided gates and devices obtained thereof

1 . A method of manufacturing a fully-silicided-gate electrode in a semiconductor device, comprising:

depositing a metal layer over a semiconductor layer of a gate stack;

providing a first thermal budget to allow a partial silicidation of said semiconductor layer, wherein a silicide layer obtained has a metal-to-semiconductor ratio greater than one;

selectively removing a remaining unreacted metal layer; and

providing a second thermal budget to allow a full silicidation of said semiconductor layer.

2 . A method according to claim 1 , wherein said semiconductor layer comprises at least one of silicon and germanium.

3 . A method according to claim 1 , wherein said semiconductor layer comprises poly-silicon.

4 . A method according to claim 1 , wherein said metal layer comprises at least one of a refractory metal, a noble metal, a transition metal, and a combination thereof.

5 . A method according to claim 1 , wherein said metal layer comprises Ni.

6 . A method according to claim 1 , wherein said first thermal budget is determined by a silicidation kinetics graph generated for each silicide phase, M x S y envisioned in the partially silicided semiconductor layer, wherein M represents said metal layer and S said semiconductor layer used, and wherein x and y are real numbers greater than zero.

7 . A method according to claim 1 , wherein providing said first thermal budget consists of a Rapid Thermal Processing (RTP).

8 . A method according to claim 1 , wherein providing said second thermal budget consists of a Rapid Thermal Processing (RTP).

9 . A method according to claim 1 , wherein selectively removing said remaining unreacted metal layer consists of a selective etching.

10 . A method according to claim 1 , wherein said metal layer consists of Ni and said semiconductor layer consists of poly-silicon.

11 . A method according to claim 10 , wherein said first thermal budget is provided such that an Ni 2 Si layer is grown having a thickness between 0.9 and 1.5 of the poly-silicon thickness, thereby forming a NiSi FUSI gate.

12 . A method according to claim 11 , further comprising generating a silicidation kinetics graph for Ni 2 Si, whereby the temperature and time period to apply said first thermal budget is determined.

13 . A method of manufacturing a fully-silicided-gate electrode in a MOSFET device, comprising:

depositing a nickel layer over a poly-silicon layer of a gate stack;

providing a first thermal budget to allow a partial silicidation of said poly-silicon layer, wherein a silicide layer obtained has a nickel/silicon ratio greater than one;

selectively removing a remaining unreacted metal layer; and

providing a second thermal budget to allow a full silicidation of said semiconductor layer.

14 . A method according to claim 13 , wherein said first thermal budget is determined by a silicidation kinetics graph generated for each silicide phase, Ni x Si y , envisioned in the partially silicided gate, wherein x and y are real numbers greater than zero, and wherein 1<x/y≦3.

15 . A method according to claim 13 , wherein providing said first thermal budget consists of an Rapid Thermal Processing (RTP).

16 . A method according to claim 13 , wherein providing said second thermal budget consists of an Rapid Thermal Processing (RTP).

17 . A method according to claim 13 , wherein removing said remaining unreacted metal layer consists of a selective etching.

18 . A method according to claims 17 , wherein said first thermal budget is provided such that a Ni 2 Si layer is grown having a thickness between 0.9 and 1.5 of the poly-silicon thickness, thereby forming a NiSi FUSI gate.

19 . A method according to claim 18 , further comprising generating a silicidation kinetics graph for Ni 2 Si, whereby the temperature and time period to apply said first thermal budget is determined.

20 . A method according to claim 13 , wherein said poly-silicon layer is on at least one of a SiON layer and a HfSiON layer.