Semiconductor device having cell transistor with recess channel structure

1. A semiconductor device comprising:

a semiconductor silicon substrate;

device separation portions provided at predetermined positions on said semiconductor silicon substrate;

a cell transistor having a recess channel structure being provided at a first region at said semiconductor silicon substrate defined by said device separation portions;

a peripheral transistor having an nMOSFET structure being provided at a second region at said semiconductor silicon substrate defined by said device separation portions; and

a peripheral transistor having an pMOSFET structure being provided at a third region at said semiconductor silicon substrate defined by said device separation portions,

(A) said cell transistor having the recess channel structure comprising:

(1) a recess provided at a predetermined position on said semiconductor silicon substrate;

(2) a gate insulating film provided in contact with an inside of the recess;

(3) a gate electrode having an N-type polysilicon layer provided in contact with the gate insulating film and a conducting layer provided in contact with the N-type polysilicon layer; and

(4) a pair of source/drain regions including N-type diffusion layers provided at both sides of the gate electrode on a surface region of said semiconductor silicon substrate,

(B) said peripheral transistor having the nMOSFET structure provided at the second region, having:

(5) a gate insulating film provided at a predetermined position on said semiconductor silicon substrate;

(6) a gate electrode having an N-type polysilicon layer provided in contact with the gate insulating film and a conducting layer provided in contact with the N-type polysilicon layer; and

(7) a pair of source/drain regions including N-type diffusion layers provided at both sides of the gate electrode on a surface region of said semiconductor silicon substrate,

(C) said peripheral transistor having the pMOSFET structure provided at the third region, having:

(8) a gate insulating film provided at a predetermined position on said semiconductor silicon substrate;

(9) a gate electrode having a P-type polysilicon layer provided in contact with the gate insulating film and a conducting layer provided in contact with the P-type polysilicon layer; and

(10) a pair of source/drain regions including P-type diffusion layers provided at both sides of the gate electrode on a surface region of said semiconductor silicon substrate, the N-type polysilicon layer in said cell transistor containing an N-type impurity at an approximately constant concentration.

2. The semiconductor device according to claim 1 , wherein the gate electrode included in the cell transistor having the recess channel structure comprises: the N-type polysilicon layer provided in contact with the gate insulating film; and the conducting layer provided in contact with the N-type polysilicon layer inside the recess and over the recess.

3. The semiconductor device according to claim 2 , wherein a concentration of the N-type impurity contained in the N-type polysilicon layer in the cell transistor having the recess channel structure ranges from 1.0×10 20 to 1.0×10 21 /cm 3

4. The semiconductor device according to claim 1 , wherein the gate electrode included in the cell transistor having the recess channel structure comprises: the N-type polysilicon layer provided in contact with the gate insulating film; a second polysilicon layer provided inside the N-type polysilicon layer and having an impurity concentration of less than 1.0×10 20 /cm 3 ; and the conducting layer provided in contact with the N-type polysilicon layer.

5. The semiconductor device according to claim 4 , wherein a concentration of the N-type impurity contained in the N-type polysilicon layer in the cell transistor having the recess channel structure ranges from 1.0×10 20 to 1.0×10 21 /cm 3 .

6. The semiconductor device according to claim 1 , wherein the gate electrode included in the cell transistor having the recess channel structure comprises: the N-type polysilicon layer provided in contact with the gate insulating film and all over the inside of the recess; and the conducting layer provided in contact with the N-type polysilicon layer.

7. The semiconductor device according to claim 6 , wherein a concentration of the N-type impurity contained in the N-type polysilicon layer in the cell transistor having the recess channel structure ranges from 1.0×10 20 to 1.0×10 21 /cm 3 .

8. The semiconductor device according to claim 1 , wherein a concentration of the N-type impurity contained in the N-type polysilicon layer in the cell transistor having the recess channel structure ranges from 1.0×10 20 to 1.0×10 21 /cm 3 .

9. A semiconductor device having a memory that includes a cell transistor, a first peripheral transistor and a second peripheral transistor; comprising:

a semiconductor substrate; and

a device separation portion selectively formed in the semiconductor layer to define first, second and third regions;

said cell transistor being formed in the first region and comprising an N-channel MOSFET that includes;

a recess selectively formed in the first region to define first surface portion and a second surface portion apart from each other,

a pair of source/drain regions formed respectively in the first and second surface portions of the first region,

a gate insulating film formed on the recess, and

a gate electrode having an N-type polysilicon layer formed on the gate insulating film,

said first peripheral transistor being formed in the second region and comprising an N-channel MOSFET that includes as a surface channel type a gate electrode having an N-type polysilicon layer, and

said second peripheral transistor being formed in the third region and comprising a P-channel MOSFET that includes as a surface channel type a gate electrode having a P-type polysilicon layer.

10. The device as claimed in claim 9 , wherein the gate electrode of the cell transistor further has a first conducting layer formed in contact with the N-type polysilicon layer to fill the recess, the gate electrode of the first peripheral transistor further having a second conducting layer formed in contact with the N-type polysilicon layer, and the gate electrode of the second peripheral transistor further has a third conducting layer formed in contact with the P-type polysilicon layer.

11. The device as claimed in claim 9 , wherein the N-type polysilicon layer is a first N-type polysilicon layer and the gate electrode of the cell transistor further has a second N-type polysilicon layer in contact with the first N-type polysilicon layer to fill the recess and a first conducting layer formed in contact with the first and second N-type polysilicon layers, the gate electrode of the first peripheral transistor further having a second conducting layer formed in contact with the N-type polysilicon layer, and the gate electrode of the second peripheral transistor further having a third conducting layer formed in contact with the P-type polysilicon layer.

12. The device as claimed in claim 11 , wherein the memory is a Dynamic Random Access Memory.

13. The device as claimed in claim 11 , wherein the N-type polysilicon layer in said cell transistor containing an N-type impurity at an approximately constant concentration.

14. The device as claimed in claim 9 , wherein the memory is a Dynamic Random Access Memory.

15. The device as claimed in claim 9 , wherein the N-type polysilicon layer in said cell transistor containing an N-type impurity at an approximately constant concentration.