Chip information managing method, chip information managing system, and chip information managing program
View Patent ↗In replacing word lines having defective addresses with redundant word lines, information is held in a relationship between the word lines and the redundant word lines. In other words, information is held in a replacement rule. With this arrangement, information such as a lot number, a wafer number within the lot, and a position of a chip within the wafer can be held in the chip, without increasing the chip area at all and without using a large database.
1. A chip information management method for storing chip information into a semiconductor chip itself that includes a memory cell array having a plurality of memory cells, a plurality of defective address storing circuits each of which can store a defective address, and a redundant memory cell array that can replaces memory cells corresponding to defective addresses stored in the defective address storing circuits, the chip information management method comprising:
a first step of detecting a plurality of defective addresses;
a second step of determining a relationship between the plurality of defective addresses and the plurality of defective address storing circuits that store the defective addresses, based on the chip information to be stored; and
a third step of storing the defective addresses in the corresponding defective address storing circuits, based on the relationship determined at the second step.
2. The chip information management method as claimed in claim 1 , wherein
at the second step, a magnitude correlation of defective addresses stored in the defective address storing circuits along a layout order is linked to the chip information to be stored.
3. The chip information management method as claimed in claim 2 , wherein
the second step is performed by determining which defective addresses are stored in which defective address storing circuits, by referring to a data table that shows a relationship between a replacement rule and corresponding information.
4. The chip information management method as claimed in claim 1 , wherein
at the first step, an address of a defective memory cell and an address of a part of memory cells having no defect are detected as the defective addresses.
5. The chip information management method as claimed in claim 4 , wherein
the part of memory cells having no defect are detected by gradually increasing a refresh cycle in an operation test of the memory cell array.
6. The chip information management method as claimed in claim 1 , wherein
at least a part of the plurality of defective address storing circuits is divided into a plurality of sub-groups, and at least two sub-groups have the same chip information.
7. The chip information management method as claimed in claim 1 , wherein
the chip information includes position information of the semiconductor chip on a wafer.
8. A chip information management method for obtaining chip information stored in a semiconductor chip that includes a memory cell array having a plurality of memory cells, a plurality of defective address storing circuits each of which can store a defective address, and a redundant memory cell array that can replaces memory cells corresponding to defective addresses stored in the defective address storing circuits, the chip information management method comprising:
a first step of reading addresses stored in the plurality of defective address storing circuits by a roll call test;
a second step of specifying a replacement rule of the redundant memory cell array, by analyzing which addresses are stored in which defective address storing circuits; and
a third step of specifying the chip information, based on a specified replacement rule.
9. The chip information management method as claimed in claim 8 , wherein
at the second step, a replacement rule of the redundant memory cell array is specified, by analyzing a layout order of the plurality of defective address storing circuits and a magnitude correlation of stored addresses.
10. The chip information management method as claimed in claim 8 , wherein
at the third step, the chip information is specified, by referring to a data table that shows a relationship between a replacement rule of the redundant memory cell array and corresponding information.
11. The chip information management method as claimed in claim 8 , wherein
at least a part of the plurality of defective address storing circuits is divided into a plurality of sub-groups, and
at the first step, when an address cannot be read from at least one of defective address storing circuits that constitute a predetermined sub-group, an address is read from a defective address storing circuit that constitutes other sub-group.
12. The chip information management method as claimed in claim 8 , wherein
the chip information includes position information of the semiconductor chip on a wafer.
13. A chip information management system comprising:
a chip information obtaining unit that obtains chip information of a semiconductor chip; and
a replacement rule determining unit that determines defective address storing circuits of the semiconductor chip into which a plurality of defective addresses included in the semiconductor chip are to be stored, wherein
the replacement rule determining unit differentiates a magnitude correlation of defective addresses along a layout order of the plurality of defective address storing circuits, based on the chip information obtained by the chip information obtaining unit.
14. The chip information management system as claimed in claim 13 , wherein
the replacement rule determining unit determines defective address storing circuits into which a plurality of detected defective memory addresses are to be stored, by referring to a data table that shows a relationship between a replacement rule according to the redundant memory cell array within the semiconductor chip and corresponding information.
15. A chip information management system comprising:
a roll call unit that reads defective addresses of a semiconductor chip, by a roll call test; and
an analyzing unit that analyzes a relationship between defective addresses read out by the roll call unit and a layout order of defective address storing circuits within the semiconductor chip that stores the defective addresses, wherein
the analyzing unit specifies chip information from the analyzed relationship, by referring to a data table that shows a relationship between a replacement rule according to the redundant memory cell array within the semiconductor chip and corresponding information.
16. A chip information management program that makes a computer execute
a first step of obtaining chip information of a semiconductor chip, and
a second step of determining defective address storing circuits of the semiconductor chip into which a plurality of defective addresses included in the semiconductor chip are to be stored, wherein
at the second step, a magnitude correlation of defective addresses along a layout order of the plurality of defective address storing circuits is differentiated, based on the chip information.
17. A chip information management program that makes a computer execute
a first step of reading addresses stored in defective address storing circuits within a semiconductor chip, by a roll call test; and
a second step of analyzing a relationship between the addresses and a layout order of the defective address storing circuits that store the addresses, wherein
at the second step, chip information is specified from the analyzed relationship, by referring to a data table that shows a relationship between a replacement rule according to the redundant memory cell array within the semiconductor chip and corresponding information.