Circuit for asynchronously resetting synchronous circuit
View Patent ↗A reset signal generation circuit for generating a reset signal synchronously or asynchronously to a clock signal in accordance with an operation state. An operation detection circuit detects operation of a CPU and generates an operation detection signal. A signal control circuit generates a first reset signal synchronously or asynchronously to an internal clock signal based on the operation detection signal and a system reset signal. The first reset signal is provided to synchronous circuits including the CPU.
1. A reset signal generation circuit for generating a first reset signal provided to a synchronous circuit that operates in accordance with a clock signal, the reset signal generation circuit comprising:
an operation detection circuit for detecting whether the synchronous circuit is operating normally or abnormally and for generating an operation detection signal; and
a signal control circuit, connected to the operation detection circuit, for generating the first reset signal based on a system reset signal, the clock signal, and the operation detection signal,
wherein the signal control circuit generates the first reset signal that is synchronous to the clock signal in response to the system reset signal when the synchronous circuit is operating normally, and
wherein the signal control circuit generates the first reset signal that is asynchronous to the clock signal in response to the system reset signal when the synchronous circuit is operating abnormally.
2. The reset signal generation circuit according to claim 1 , further comprising:
an asynchronous circuit responsive to a second reset signal that is asynchronous to the clock signal, wherein the signal control circuit generates the second reset signal based on the system reset signal.
3. The reset signal generation circuit according to claim 1 , wherein the signal control circuit generates the first reset signal based on the operation detection signal and a voltage detection signal indicating a decrease in power supply voltage.
4. The reset signal generation circuit according to claim 2 , further comprising:
a power on reset circuit, connected to the signal control circuit, for generating a power on reset signal for stopping operation of the synchronous circuit and the asynchronous circuit until the power supply voltage reaches a predetermined voltage, wherein the signal control circuit generates the second reset signal in response to the power on reset signal.
5. The reset signal generation circuit according to claim 2 , wherein the signal control circuit includes:
a gate circuit, connected to the operation detection circuit, for generating the second reset signal based on the operation detection signal and the system reset signal; and
a flip-flop circuit, connected to the gate circuit, for generating the first reset signal according to the system reset signal in synchronism with the clock signal when the second reset signal has a first level and for generating the first reset signal asynchronously to the clock signal when the second reset signal has a second level, which is an inverted level of the first level.
6. The reset signal generation circuit according to claim 1 , wherein the signal control circuit receives a voltage detection signal indicating a decrease in power supply voltage and generates the first reset signal that is asynchronous to the clock signal in response to the system reset signal when the power supply voltage is lower than a predetermined voltage.
7. The reset signal generation circuit according to claim 1 , further comprising:
a power on reset circuit which generates a power on reset signal for stopping operation of the synchronous circuit until power supply voltage reaches a predetermined voltage,
wherein the signal control circuit generates the first reset signal that is asynchronous to the clock signal in response to the system reset signal when operation of the synchronous circuit is stopping by the power on reset signal.